Abstract: A power metal oxide semiconductor-field-effect-transistor (MOSFET) device using trench technology to achieve a reduced-mask-production process. The power MOSFET device includes a gate signal bus having multiple gate trenches formed using fewer masks than previously required for a similar device. The two-dimensional behavior of the trenches provides an advantageous field-coupling effect that suppresses hot-carrier generation without the need for the commonly used thick layer of silicon dioxide beneath the gate polysilicon. The use of easily controlled silicon trench etching in production of the power MOSFET results in stable, low cost, and high yielding manufacturing.

Abstract: An improved digester apparatus converts wet carbonaceous biomass materials to biogas in a digestion unit operating at a controlled temperature and having a concentrator component and a pressure swing component each containing anaerobic bacteria. The apparatus conveys slurried aqueous biomass from a biomass source to the concentrator component and removes the biogas from the concentrator component and conveys concentrated aqueous biomass from the concentrator component to the pressure swing component and conveys digested aqueous biomass from the pressure swing component to the concentrator component. The apparatus removes waste solids from the pressure swing component and a pressure swing pump controls the pressure within the pressure swing component in a cycle comprising a sub-atmospheric first pressure phase and a second pressure phase at or above atmospheric pressure.

Abstract: A method for generating a 3-D model of a person's face is disclosed. The 3-D face model carries both the geometry (shape) and the texture (color) characteristics of the person's face. The shape of the face model is represented via a 3-D triangular mesh (geometry mesh), while the texture of the face model is represented via a 2-D composite image (texture image). The geometry mesh is obtained by deforming a predefined standard 3-D triangular mesh based on the dimensions and relative positions of the person's facial features, such as eyes, nose, ears, lips, chin, etc. The texture image is obtained by compositing a set of 2-D images of the person's face which are taken from particular directions such as front, right, left, etc, and modifying them along region boundaries to achieve seamless stitching of color on the 3-D face model. The directional images are taken while the mouth is closed and the eyes are open.

Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a delayed clock signal. The forward delay circuit adjustably shifts in time the delayed clock signal relative to the reference clock signal. An inverter receives the delayed clock signal and issues an inverted delayed clock signal. A feedback delay circuit receives a selected one of the delayed and the inverted delayed clock signals, and issues a feedback clock signal that is shifted in time relative to the selected one of the delayed and the inverted delayed clock signals. The feedback clock signal is compared to the reference clock signal. The time shift of the delayed clock signal is adjusted to thereby time-align the reference clock signal and the feedback clock signal.

Abstract: Increasing the number of MOSFET gate bump contacts makes MOSFET gate contacts more durable and reliable. Extension of the under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads overlying the source pad metallization reduces the risk of delamination of the metallization due to thermal and mechanical stresses in assembly and operation. Use of more than one gate pad further reduces such failure risks. The result is a reliable, durable MOSFET gate contact.

Abstract: An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches.

Abstract: Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.

Abstract: Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

Abstract: A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.

Abstract: A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

Abstract: Careful repositioning of MOSFET gate contacts and increasing of their number makes MOSFET gate contacts more durable and reliable without requiring changes in either the leadframe design or the assembly process. Extension of the under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads not overlying the gate pad metallization minimizes the risk of delamination of the metallization due to thermal and mechanical stresses in assembly and operation. Use of more than one gate pad further reduces such failure risks. Positioning the gate pads sufficiently close to the original gate contact permits use of the same leadframe design and assembly process as would be used for a single gate pad placed directly over the gate contact. The result is a reliable, durable MOSFET gate contact compatible with current assembly methods.

Abstract: A more robust mechanical connection is provided between a semiconductor device and the device package by adding one or more bumps to the gate connection without adding more gate pad area. A nonconductive layer covers the area around the gate pad and extends over the source area. One or more bumps fabricated on the nonconductive layer provide mechanical strength and support to the gate pad connection. The added bumps are not electrically connected to either the gate or the source. The package connections must be altered, both to fit the added bumps on the control gate, and to connect with fewer bumps on the source.

Abstract: An improved MOS-gated power device 300 with a substrate 101 having an upper layer 101a of doped monocrystalline silicon of a first conduction type that includes a doped well region 107 of a second conduction type. The substrate further includes at least one heavily doped source region 111 of the first conduction type disposed in a well region 107 at an upper surface of the upper layer, a gate region 106 having a conductive material 105 electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer 112 on the upper surface overlying the gate and source regions 114, and a heavily doped drain region of the first conduction type 115. The improvement includes body regions 301 containing heavily doped polysilicon of the second conduction type disposed in a well region 107 at the upper surface of the monocrystalline substrate.

Abstract: A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof. The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.

Abstract: A process forms a power semiconductor device with reduced input capacitance and improved switching speed. A substrate with an epitaxial has an oxide layer patterned to form a narrow terraced gate. A gate oxide layer is formed on the upper surface of the epitaxial layer. A layer of polysilicon is deposited on the narrow terraced gate oxide region and the gate oxide layer. The polysilicon layer is anisotropically etched to form polysilicon spacers abutting each of the two side surfaces of the narrow terraced gate region. A p-type dopant is implanted through the gate oxide layer and the polysilicon spacers and is driven in to form P-well regions in the epitaxial layer. A source mask is formed and an n-type dopant is implanted through the gate oxide layer and the polysilicon spacers. It is driven in to form N+ source regions in the P-well regions.

Abstract: A method of analyzing an electrocardiogram (ECG) paper chart includes the steps of scanning the ECG chart, to thereby create a computer-readable ECG image file representative of the ECG chart, storing the ECG image file in a memory of a computer, opening the ECG image file and displaying on a computer display an ECG plot corresponding to the ECG image file, calibrating the x-axis and y-axis of the displayed ECG plot with an x-axis scale and a y-axis scale, identifying characteristics of the ECG plot by using an input device connected to the computer, and measuring the identified characteristics.

Abstract: A trench MOS-gated device has an upper surface and includes a substrate having an upper layer of doped monocrystalline semiconductor material of a first conduction type. A gate trench in the upper layer has sidewalls and a floor lined with a first dielectric material and a centrally disposed core formed of a second dielectric material extending upwardly from the first dielectric material on the trench floor and having lateral and top surfaces. The remainder of the trench is substantially filled with a conductive material that encompasses and contacts the lateral and top surfaces of the core of second dielectric material. A doped well region of a second conduction type overlies a drain zone of the first conduction type in the upper layer, and a heavily doped source region of the first conduction type contiguous to the gate trench and a heavily doped body region of the second conduction type are disposed in the well region at the upper surface of the device.

Abstract: A trench MOS-gated device having an upper surface includes a substrate having an upper layer of doped monocrystalline semiconductor material of a first conduction type. A gate trench in the upper layer has sidewalls and a floor lined with a first dielectric material and a centrally disposed core that is formed of a second dielectric material and extends upwardly from the first dielectric material on the trench floor to contact an interlevel dielectric layer overlying the gate trench. The remainder of the trench is substantially filled with a conductive material that encompasses and contacts the core of second dielectric material. A doped well region of a second conduction type overlies a drain zone of the first conduction type in the upper layer, and a heavily doped source region of the first conduction type contiguous to the gate trench and a heavily doped body region of the second conduction type are disposed in the well region at the upper surface.

Abstract: An improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics comprises a semiconductor substrate on which is disposed a doped upper layer of a first conduction type. The upper layer includes a doped first well region of the first conduction type and a doped well region of the second conduction type underlying the first well region. The upper layer further includes at its upper surface a heavily doped source region of the first conduction type and a heavily doped body region of a second and opposite conduction type. A trench gate comprising a conductive material separated from the upper layer by an insulating layer is disposed in the upper layer of the substrate.

Abstract: The invention relates to a circuit arrangement for energy-saving operation of a fluorescent tube (1) whereby two respective connections (2a, 2b, 3a, 3b) are arranged on the end caps (1a, 1b) of said tube. The fluorescent tube is mechanically and electrically linked to brackets (8, 9) via said connections (2a, 2b, 3a, 3b) and can be connected to an alternating current supply (6) via a reactance coil (4) and a starter (5). The objective of the invention is to allow the fluorescent tube to be retrofitted in a simple manner. This is achieved by means of a quadrupole (4) circuit arrangement, whereby the input terminals (7a, 7b) of said quadrupole form a series connection with the two connections (2a, 2b, 3a, 3b) on one end cap (1a, 1b) and the reactance coil (4), whereby said circuit is connected in parallel to the alternating current source (6), and the output terminals (7c, 7d) of said quadrupole are electrically connected to the two connections (3a, 3b, 2a, 2b) on the other end cap (1b, 1a).