Abstract: Solar cells are formed of semi-conductor spheres of P-type interior having an N-type skin are pressed between a pair of aluminum foil members forming the electrical contacts to the P-type and N-type regions. The aluminum foils, which comprise 1.0% silicon by weight, are flexible and electrically insulated from one another. The spheres are patterned in a foil matrix forming a cell. Multiple cells can be interconnected to form a module of solar cell elements for converting sun light into electricity.
July 31, 1989
Date of Patent:
March 9, 1993
Texas Instruments Incorporated
Sidney G. Parker, Milfred D. Hammerbacher, Jules D. Levine, Gregory B. Hotchkiss
Abstract: A two transistor gain-type DRAM cell (8) is formed in a trench (30) to optimize wafer area requirements. Formed on a heavily doped semiconductor substrate (20) are alternate layers of P-type and N-type semiconductor material defining the elements of a vertical pass transistor (12) and gain transistor (24). A trench is formed through the alternate semiconductor layers into the substrate (20), and filled with two regions of a semiconductor material defining a storage node (18) and, insulated therefrom, a word line (16). The gain transistor (24) is fabricated having a response time faster than that of the pass transistor (12) so that, during read operations, the gain transistor (24) changes the precharged voltage of the read bit line (26), depending upon the charge stored in the capacitor storage node (18).
Abstract: A technique for analyzing defective semiconductor chips is disclosed. The silicon substrate of the chip is etched away, leaving the memory cells exposed for viewing. The method includes the steps of: removing oxide from the backside of a semiconductor device; and, placing the semiconductor device into a solution of choline and water. The solution etches away the substrate. The memory cells may be photographed and viewed by TEM and SEM techniques.
Abstract: A circuit for reducing the metastable events produced by a data signal asynchronous to a system clock signal is provided. The circuit includes an edge detector (32) for detecting a transistion of the data signal. The edge detector (32) controls a clock disable/reenable circuit (46) which will disable a system clock directed to a clocked device (36). The period of disablement is the minimum setup time for the clocked device (36). After the minimum setup time has passed, the disable/reenable circuit (42) will reenable the system clock to the clocked device (36). The system clock may be modified by a duration limit circuit (68). Data directed to the clocked device (36) may be delayed via a delay circuit (70).
Abstract: A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold.
Abstract: A circuit for use as a TTL level CMOS input buffer with hysteresis is disclosed. A first transistor of a first conductivity tupe has its source connected to a first reference voltage. Second and third transistors of opposite conductivity type have their source drain paths connected in series between the drain of the first transistor and a common potential. The gates of the first, second, and third transistors are connected to an input signal. An inverter has its input connected to the drain of the first transistor and has an output. A fourth transistor of the first conductivity type has its gate connected to the output, its drain connected to the series connection between the second and third transistors, and its source connected to a second reference voltage. By appropriately sizing the transistors, the low level trip point and the high level trip point of the circuit may be adjusted. The circuit draws low power during standby. Logic gates may also be designed that incorporate the circuit.
Abstract: A memory array layout using complementary bitlines connected to a single sense amplifier. Extending from the sense amplifier, bitlines which are unconnected are extended to the middle of the array. One complementary bitline is then connected to a series of memory cells extending away from the sense amplifier. The other complementary bitline loops back and is connected to a set of memory cells extending back toward the sense amplifier. The first bitline section extending from the sense amplifier may be advantageously formed in a metal layer above the substrate thereby occupying no space in the substrate itself. All noise generated on the first sections of the bitlines will be canceled by the complementary parallel structure of the bitlines. Because the second sections of the bitlines are laterally separated, a wordline passing across each of the second sections addresses a singel memory cell. Therefore an optimally compact cross-point memory array may be fabricated.
Abstract: A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme.
September 22, 1989
Date of Patent:
July 16, 1991
Texas Instruments Incorporated
Bimal Pathak, Steven P. Marshall, James F. Potts
Abstract: A sense amplifier (10) has P channel transistors (38,48) connected between first and second nodes (34,44) of the sense amplifier and respective bitlines (12,14). The gates (42,52) of the P channel transistors (38,48) are connected to ground. As the voltage at one of the nodes (34 or 44) approaches ground voltage during the sensing operation, the bitline (12 or 14) is effectively disconnected from the sense amplifier (10) thereby increasing sensing speed while reducing noise between the bitline and the node.
Abstract: The described embodiments of the present invention provide a circuit and method for programming the mode options of an integrated circuit. The embodiment described provides this function for a dynamic random access memory but is applicable to any integrated circuit. The integrated circuit includes programming bonding pads which are either connected to a selected reference potential or left unconnected. Circuitry on the integrated circuit determines whether the pad is connected to the reference potential or is unconnected, and provides logical signals on the integrated circuit which select the operational mode of the integrated circuit. An additional feature of the described embodiment is a continuous checking to determine if the appropriate connected or unconnected state is being detected. This feature prevents stray fields and other erroneous signals from altering the mode operation of the integrated circuit.
Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The four sides of the floating gates are defined with a single patterning step.
Abstract: A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value.
January 11, 1988
Date of Patent:
June 4, 1991
Texas Instruments Incorporated
Jy-Der Tai, Edison Chiu, Quang-Dieu An, Te-Chuan Hsu
Abstract: A method for measuring the access time or speed of PROM devices is described. The PROM (10) includes a matrix of erased memory cells (30-70) each selectable by an address, and readable by a sense amplifier (112). The method comprises providing an invalid address and reading the level at the sense amplifier (112). A valid address is then provided, and the memory cell addressed is read. The above steps are repeated until all memory cells are read. In this manner, the time required to access an erased memory cell after accessing a programmed memory cell, as simulated by a nonexistent memory cell, may be measured.
Abstract: Apparatus for decoding a plurality of electrically programmable memory cells (30-70) comprises an array source driver circuit (72) for selectively connecting a first terminal (140) of a selected memory cell (152) to a program bias voltage or to ground. A bit line driver circuit (94-100, 120) selectively connects a second terminal (154) of said selected memory cell (152) to ground or to a read sense node (115). Reading is performed by connecting the first terminal (140) to ground and the second terminal (154) to the read sense node (115). Programming is performed by connecting the first terminal (140) to the program bias voltage and the second terminal (154) to ground.
Abstract: The process of this invention includes forming and patterning a first layer of photoresist to form first lines of photoresist having substantially minimum lithographic widths, forming first elements between the first lines of photoresist, removing the photoresist, forming a sidewall member on each side edge of the first elements, forming a second layer over the structure, and etching to electrically insulate the first elements and the second elements at the sidewalls. Alternatively, the structure is coated with another layer of photoresist after formation of sidewall member on each side of the first elements. The layer of photoresist is patterned to form second photoresist lines that cover alternating sidewall members. The exposed sidewall members are removed. Strips are formed between the second photoresist lines. After removal of the second photoresist lines, the structure is etched as before. However, in this embodiment, lateral extensions of the first elements are formed.
Abstract: A transistor structure is disclosed which has a vertical channel which has its length controllable by currently-used diffusion processes, and which occupies a minimum of silicon surface area. The transistor is constructed by using a triple-level implant and diffusion process. The drain region is diffused into the silicon area by way of ion implantation and subsequent diffusion. The channel region, of opposite conductivity-type from the drain region, is implanted and diffused into the drain region. The source region is similarly implanted, and diffused into the channel region. A trench is etched into the silicon, extending through the source, channel and drain regions; gate oxide is grown in the trench and a polysilicon gate is deposited in the trench, conformal with the gate oxide. Transistor action takes place in the channel region along the walls of the trench, dependent upon the voltage applied to the gate electrode.
Abstract: An electrically erasable, progammable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.
Abstract: A pair of like, semiconductor integrated circuit bars, such as DRAMS, have second level bonding pads formed over their active surfaces in mirror images of one another. The bars then become bonded to opposite sides of frame bonding pads of a lead frame to double the capacity of a normally encapsulated integrated circuit. The normal bar bonding pads of the circuit bars are arranged identical to one another, and a patterned and etched second level of metal forms second level lands over the bar bonding pads, the mirror image second level bonding pads and second level leads connecting corresponding second level lands to second level pads. A pair of 256K DRAMS can be connected either 256K.times.2 or 512K.times.1 by use of dummy second level pads for DATA-IN/OUT and ROW ADDRESS STROBE connection.
Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells with a different sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects a segment to be connected to the bit line. The ratio of storage capacitance to effective bit line capacitance is increased, because the bit line itself is of lower capacitance to the substrate.
Abstract: A CMOS sense amplifier for a dynamic read/write memory employs a latch circuit with cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through P and N channel transistors selectively activated by sense clocks. Differential inputs of the sense amplifier are connected to the bit lines. The N-channel transistors are employed for initial sensing, and then both N-channel and P-channel transistors in sequential order for amplification and restoring the I-level. This results in better balance, and smaller N and P channel latch transistors may be used, saving area, saving power and increasing speed.