Abstract: An integrated-circuit memory-array configuration for providing less total access time when used in conjunction with a microprocessor. The configuration includes a line buffer with perhaps 256 latches for storing data, and first and second pipeline circuits for sensing linearity and locality of access information pertaining to the requested data. When used with a microprocessor that is programmed with repeated requests for the same data, a majority of the data requests will be transmitted quickly from the line buffer. If the data requests are not in the line buffer, the configuration furnishes a signal to the microprocessor and the requested data are moved from the floating-gate memory cell array to the line buffer for subsequent transmittal to the microprocessor.
Abstract: A content addressable memory consists of a plurality of memory units each of which may be an integrated circuit. Each unit receives an input group of digits forming all or part of an input key code, and compares it simultaneously with a plurality of equally sized groups of digits stored in the memory of the unit. The memory of a unit has 32K bytes of storage elements functionally arranged in 512 rows and column. The 64 bytes forming a row are each compared with an input group of 8 binary digits. A status bit is produced for each of the 64 bytes of a row and indicates whether or not the input group matches the particular byte. The match need not be perfect and certain digits may be masked so that comparison of them does not detract from the match assessment. The status bits are combined logically to produce higher and higher order status bits selectively indicating the presence of a match in larger and larger groups of storage elements up to the entire memory of the unit.
Abstract: A split bonding pad provides a positive electrical indication of the proper electrical and mechanical connection of a capacitor to a printed circuit board by placing the electrical component terminal in series with electrical power supplied to a memory device while the electrical component remains in parallel connection with the memory device power lead. The proper mounting of the electrical component to the board becomes testable by testing continuity of a series circuit through the leads extending to the split bonding pad.
Abstract: A semiconductor device is programmed by a laser beam which causes a PN junction in a silicon substrate to be permanently altered. This produces a leakage path between a program node and a tank region in the substrate; the program node can be an input to a transistor in a CMOS circuit, for example, so this node will always hold the transistor on or off depending whether or not it has been laser-programmed. Preferably, the tank region is of opposite type compared to the substrate, so the program node is electrically isolated from the substrate in either case.
Abstract: A dynamic random access memory cell array is disclosed which has storage capacitors and access transistors formed on the sidewalls of pillars created by trenches etched into the face of a semiconductor bar. A storage capacitor for a cell uses the sidewalls of the pillar as one plate and a polysilicon plug or web as the other plate. The channel of each access transistor is formed in the upper part of the sidewall of only a portion of the pillar, using an upper edge of the capacitor region as the source region of the transistor and having an N+ drain region at the top of the pillar. A cross-point array is made possible by merging two adjacent wordlines as a pair of overlying conductor strips extending along the face over the trenches, between pillars, and forming the transistor gates by alternate protrusions from these strips, extending down into the trenches at the channel area.
Abstract: A DRAM array having a number of two-port cells (10) arranged to permit the simultaneous read and write operations of different cells within the array. Each column of the array includes a refresh circuit (40) which is responsive to a four-phase clock for carrying out refresh operations which are transparent to the programmer. When used in microcomputer applications having four-phase clocks, the DRAM array of the invention functions similar to a static RAM, in that refresh is automatically undertaken.
Abstract: A contact and interconnect for an MOS VLSI semiconductor device employs a contact hole in an insulator coating; the contact hole has vertical instead of sloped sidewalls. A first metallization is applied by CVD so that the sidewalls will be coated to a uniform thickness, then this first metal is anisotropicalloy etched to leave metal sidewalls. A second metallization is applied by sputtering or evaporation, which provides a more dense and electromigration-resistant coating. A refractory metal layer may be interposed between the metallization and the silicon substrate, and also between the metal interconnect and the insulator, since the insulator usually contains phosphorus.
Abstract: A two transistor gain-type dynamic random access memory (DRAM) cell (8) formed in a trench (30) to optimize wafer area requirements. Formed on a heavily doped semiconductor substrate (20) are alternate layers of P-type and N-type semiconductor material defining the elements of a vertical pass transistor (12) and gain transistor (24). A trench is formed through the alternate semiconductor layers into the substrate (20), and filled with two regions of a semiconductor material defining a storage node (18) and, insulated therefrom, a word line (16). The gain transistor (24) is fabricated having a response time faster than that of the pass transistor (12) so that, during read operations, the gain transistor (24) changes the precharged voltage of the read bit line (26), depending upon the charge stored in the capacitor storage node (18).
Abstract: The disclosure relates to an electrical connection between a bonding pad on a semiconductor chip and a wire wherein the bonding pad is formed of copper doped aluminum and the wire is formed of copper doped gold. The wire has from about 100 to about 10,000 parts per million copper and the pad has from about 5000 to about 50,000 parts per million copper.
Abstract: A printed circuit board or other substrate mounts electrical components substantially coplanar with the median plane or thickness of the board or substrate. The board furnishes an opening having bonding pads plated through the opening and fixed on the opposite sidewalls of the opening. The electrical component becomes placed in the the opening with solder paste between the bonding pads and end terminals of the electrical component. Reflow soldering techniques melt the solder paste into solder filets that solidify to fasten the electrical component within the opening in coplanar with the median plane or thickness of the board.
Abstract: A method and structure for adjustment of the threshold voltage of a vertical metal-oxide-semiconductor transistor. Chemical vapor deposition of doped silicon dioxide and annealing are used to form a voltage-threshold-adjustment region in at least the channel layer of the transistor adjacent to the trench wall.
Abstract: In semiconductor processing, it is desirable to protectively cover the wafer (40) prior to sawing the wafer (40) into individual chips. The compressive nitride protective cover tends to bow the normally flat surface of the wafer (40). If the compressive stress is too great, the wafer (40) and the circuits thereon may be damaged. The laser stress measurement apparatus (10) provides a method for checking the wafer (40) for excess stress without destroying the wafer (40). A light source (12) emits a beam of light onto a reflector (22) which reflects the light onto wafer (40). The light is deflected by wafer (40) back to the reflector (22) and thence to a light detector (52). The light detector (52) is positioned to receive the light in an exact center such that subsequent readings may be taken to determine a change in deflection. The change in deflection is then used in a formula to determine the compressive stress on wafer (40).
Abstract: A microcomputer is disclosed which provides for a dedicated DMA data and address bus connecting an on-chip DNA controller with on-chip memories, and with on-chip ports for access to external memory and input/output devices. The DMA controller contains a control register which has two start bits, capable of representing four start codes. The four start codes allow for the unconditional starting and aborting of a DMA transfer, as well as for stopping the DMA after the current read or write operation, or after the next write operation (i.e., completion of a data word transfer). The control register also contains two status bits which the DMA controller writes with the status of the DMA operation, and also contains two synchronization bits for synchronizing the DMA operation in the source, destination, or source and destination modes (or not at all). Two interrupt enable registers are provided in the microcomputer, for independently enabling interrupts for the CPU and the DMA.
Abstract: The described embodiments of the present invention provide a dynamic random access memory cell and array. The memory cell provides a three transistor storage device where the storage signal is stored on the gate of a storage transistor. All three transistors are integrated into a trench thereby providing the density equal to that of the densest of modern day DRAM cells. By using the three transistor concept, the first embodiment of the present invention provides a gain for the stored charge. Because the storage transistor amplifies the stored charge, the reduced capacitance of ultra-dense DRAM cells is overcome and adequate data sensing may be accomplished using capacitances much smaller than those useful in the single transistor, single capacitor DRAM cell.
Abstract: A process for forming backside contacts includes first forming an etch stop layer (12) beneath the surface of a silicon substrate. An active circuit is then formed in the silicon surface and associated metal interconnecting layers formed on the upper surface of the substrate. A planarizing layer is then formed on the upper surface of the substrate which is operable to be connected to a mechanical support. Thereafter, the backside of the substrate is etched away up to the etch stop layer (12). The thickness of the remaining substrate between the metal layers on the upper surface and the etch stop layer is sufficiently thin that the alignment marks on the upper surface can be seen through the substrate. These alignement marks are utilized to form vias from the backside to the active elements and then deposit and pattern interconnecting layers on the backside.
Abstract: A test circuit (40) fabricated in an integrated circuit and connected to an I/O pin (36) of the packaged device (32) for providing information indicative of substrate process parameters. The test circuit (40) comprises a test transistor (24) connected to a pin (36) of the packaged device (32), and an isolation circuit (52) responsive to a signal on an input test terminal (48) for activating the test transistor (24). The isolation circuit (52) is responsive to the absence of the test signal for isolating the test transistor (24) from the pin (36), and thus isolating it from other functional circuitry (54) of the integrated circuit which is also connected to the pin (36).
Abstract: In a dynamic random access memory (10) that includes a cell array area (12) and at least one peripheral array area (14), a plurality of sense amplifier banks (20) are arranged in rows. A plurality of elongate longitudinal signal conductors (92) are formed over the cell array area (12) to intersect each of the rows. Each row has at least one transverse signal conductor (98) that is coupled to at least some of the longitudinal signal conductors (92). Inputs of the sense amplifiers (30) in the row are coupled to the transverse signal conductor (92) for receiving the global signal. A signal driver circuit (124-130) is formed in the peripheral area (14), with the longitudinal conductors (98) coupled to outputs of the signal driver circuit (124-130).
Abstract: The described embodiment of the present invention includes a combinatorial circuit, such as a multiplexor. All or a portion of the input signals to the multiplexor are also provided to a transition detector. Upon detecting a transition, the transition detector provides a signal which temporarily suppresses the operation of the combinatorial circuit prior to a portion of the combinatorial circuit which is sensitive to glitches and/or timing errors. The delay allows time for glitches and/or timing errors to dissipate. This provides a cleaner signal for the sensitive portion to avoid the errors that the suppressed glitches and/or timing errors may cause.
Abstract: A system for real-time digital processing of a video signal is disclosed, using a large number of one-bit serial processor elements, each operating on one pixel or a horizontal scan. The video signal is converted to digital by an A-to-D converter, and stored in a set of input registers, one register for each processor element. All of these input registers are loaded during a horizontal scan, as the input registers are addressed in sequence by a commutator. Each processor element includes a one-bit binary adder, a set of one-bit registers, and two wide data memories of a size to store data from several scans. The processor elements are all controlled in common by a sequencer, a state machine or a processor. The processed video data is transferred to an output register for each processor element, from which it is converted to a video signal by a D-to-A converter.
Abstract: The described embodiments of the present invention provide an input protection device with a low trigger threshold. The structure is a silicon controlled rectifier (SCR) type of device wherein the triggering mechanism is avalanche conduction at the interface between the N-well surrounding a portion of the protection device and the P-type substrate. The embodiments provide a lowered threshold voltage by providing a highly doped region of the same conductivity type as the well at the interface between the well and the substrate. This highly doped region is connected to a resistor which is then connected to the protected node. The resistor and heavily doped region at the intersection between the N-well and substrate provides an additional source of current for avalanching at a lower voltage. Thus the trigger voltage of the protection system is substantially lowered.