Abstract: An apparatus and process for detecting aberrations in production process operations is provided. In one embodiment, operations of a plasma etch reactor (10) are monitored to detect aberrations in etching operations. A reference end-point trace (EPT) is defined (50), regions are defined in the reference EPT (52) and characteristics and tolerances for each region are defined (54). The etcher is run (56) and an actual EPT is obtained from the running of the etcher. The actual EPT is analyzed (58) by comparing characteristics of the regions of the actual EPT with characteristics of corresponding regions of the reference EPT. If the characteristics of the actual EPT exceed those of the reference EPT by predefined tolerances (62) a signal is generated (68). The system also checks for aberrations which are manifested by predefined EPT characteristics and signals when those are detected.

Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.

Abstract: An N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal silicon oxide which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel, and drain and one capacitor plate are formed essentially vertically in the sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench. Signal charge is stored on the material inserted into the trench. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface are formed as diffusions in the substrate which also form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.

Abstract: A fuse circuit for an integrated circuit chip which includes a non-volatile memory element, a circuit programmer for the memory element, and a read circuit for detecting the programmed states of the memory element and providing output signal levels corresponding to the programmed states. A switch is coupled to the read circuit output and switches from an open to a closed position in response to a selected output signal level.

Abstract: A digital processor system includes a processor, a memory and a memory interface between the processor and the memory. The memory stores data in one bit format but addresses the data in a second bit format. The interface to the memory includes a controller that is responsive to the processor, an information bus for the transfer of addresses and data and two registers to store addresses for the memory. These registers in the interface are responsive to the processor through the interface controls in order to allow the processor to increment or decrement the memory addresses or load new memory addresses from the information bus. These registers are then connected to a switch which is in turn responsive to the processor through the interface control in order that the processor can determine which register is to provide the address to the memory.

Abstract: An electrically programmable memory cell of a type having a source, a drain, a floating gate and a control gate formed over a face of a semiconductor substrate in which a ring region of material doped similarly to the substrate encloses the source, drain and gates and extends to a surface of the substrate around its length. Drain and source coupling regions of material doped oppositely to the substrate contact the drain and source, respectively, within the ring and extend under the ring to the substrate surface outside of the ring defining drain and source contact regions, respectively. A contact outside the ring to the control gate is provided by a gate coupling region also extending under the ring to a substrate surface on either side thereof. An interconnect couples the floating gate to the gate coupling region. A non-light transmitting, electrically conducting shield extends over the cell contacting the ring region around its periphery at the substrate surface.

Abstract: The present invention loads color registers of a color look up table in a color palette and recalls color data words from the color registers using only a single set of address and data channels. The color palette operates in two modes. In a normal mode one color code from a stream of pixel color codes received from a pixel map memory is employed to select one of the color registers. These color registers store color data words which define colors. A color data word stored in a selected color register is recalled and employed to control the color of a pixel on a raster scan video display. In a color look up table load mode, a predetermined number of the pixel color codes are loaded into the color look up table in a predetermined sequence, thereby defining a new set of colors. This technique multiplexes the existing data and control lines from the memory to the color palette for the two modes.

Abstract: A chemical vapor transport reactor gas dispersion disk (20) for counteracting vapor pressure gradients to provide a uniform deposition of material films on a semiconductor slice (37). The disk (20) has a number of apertures (22) arranged so as to increase in aperture area per unit of disk area when extending from the center of the disk (20) to its outer peripheral edge.

Abstract: A high efficiency dropout regulator (60) drives an output transistor (22) with a PNP transistor (52) if the overhead voltage from input (14) to output (26) is below a predetermined voltage. If the overhead voltage exceeds the predetermined voltage, then a second PNP transistor (64) and an NPN transistor (72) are used to drive the output transistor (22), resulting in a large reduction of power loss. The current drawn from the output transistor (22) by the NPN transistor (72) is returned to the output.

Abstract: A color signal is encoded into luminance and chrominance signals. Relationships between the luminance and chrominance signals, and the color components are computed. A color component signal is generated by matrixing these relationships. In addition, a signal processor may be used to combine other video images with the color component signal.

Abstract: A stacked robotic work cell process station is provided which includes first and second module chambers (14) and (26) which have associated therewith work surfaces (10) and (22). The first module chamber (14) is disposed above the work surface (22) in the second chamber (26) and staggered with respect thereto. A conduit (34) is provided for interfacing the upper surface of the chamber (26) with a point parallel to the upper surface of the first chamber (14) and adjacent thereto. A lower conduit (16) interfaces the lower portion of the first cell chamber with the lower portion of the second module chamber (26). A baffle (20) is provided for adjusting the air flow between the two chambers to provide isokinetic air flow at the upper surface of the stacked configuration.

Abstract: A plasma dry etch process for trench etching in single slice RIE etch reactors wherein a selective sidewall passivation is accomplished to control the profile of the trench being etched. The process comprises methods of passivating the sidewall by passivation on a molecular scale and by passivation by a veneer type passivation comprising buildup of a macroscopic residue over the surface of the sidewall. Several methods are disclosed for forming and shaping the passivating layers (both mono-atomic and bulk). By carefully controlling the composition and shape of the sidewall passivating veneer in conjunction with other etch factors, the desired trench profiles can be achieved.

Abstract: In a text to speech system, digital text ASCII is examined for syllable boundaries to help accent generation for speech synthesis, and hyphenation in word processing. Digital allophone code characters in the form of a byte string are compared with prestored rules. Byte string segments which may comprise consonant clusters, and left and right adjacent environments thereof are examined.

Abstract: A barrel shifter for a floating point processing unit can be optimized by having an automatic normalization feature. A multi-stage shifting unit is employed with external circuitry to verify that only leading zeros would be shifted out before activating a given shifting stage. Bit reversers are also used on the input and the output side of the barrel shifter in order to minimize the size and complexity of the circuit while still allowing bi-directional shifting.

Abstract: A non-impact printer has a movable printhead carriage for traversing a print medium and has a bracket, also serving as a heat sink, pivotally connected to the printhead carriage. A non-impact printhead is secured to the bracket and positioned to contact the print medium. A spring is positioned between the bracket and the printhead carriage to move the bracket and consequently the attached printhead into contact with the print medium. A printhead adjusting eccentric, causing relative motion between the printhead carriage and the bracket, enables vertical positioning of the printhead with respect to the print medium.

Abstract: A complex multiplier includes a carry-sum systolic array (26) of multiplier cells for processing a multiplicand therethrough in accordance with a modified Booths algorithm. The multiplier performs two multiplications and two addition/substraction operations. A ROM (12) provides the multipliers for the operation which are input to a booth decoder (50) through a delay line (48). The delay line (48) delays pairs of bits by one bit each to synchronize with the flow of the partial products through the array (26). After one product is processed in the array (26), the sum and carry is fed back to the input through a delay (52). This delay allows for processing two products in a single operation with a subsequent operation interleaved therebetween. When one operation is complete, it is output to adders (64) and (66) to perform a complex addition and substraction with another input data vector. This addition occurs at one half the rate of the pipeline (26) due to the interleaving of the two operations.

Abstract: A sweep generator for a seismic source vibrator provides for any one of a variety of sweep signals governed by input parameters. Selected analytic functions may be entered which are solved to provide a plurality of sweep parameters. The sweep parameters may also be directly entered by the operator. The time and frequency sweep parameters (or time and amplitude) are then employed to generate polynomial coefficients for consecutive use in a polynomial equation. The polynomial equation is repeatedly solved to generate a series of instantaneous frequencies or instantaneous amplitudes which are applied to an analog wave synthesizer. The analog wave synthesizer then generates an approximation to the desired sweep signal for input to the hydraulic system of the vibrator.

Abstract: A pointer, N, indicates an address in a virtual memory space of a demand paged memory including a plurality of virtual address pages and a fixed number of physical memory pages into which blocks of information can be written. A back-up memory store is provided for containing paged-out memory pages. The pointer, N, is advanced along the virtual address pages to indicate the next available virtual address page for allocation, and newly allocated blocks are located on the virtual address page pointed to by said pointer N. Should the necessary space for a block allocation not exist on the page pointed to by said pointer, N, a page which is most recently used and least sparsely utilized is identified from the physical pages onto which blocks have been previously written the block is allocated on that page. If no space remains on the virtual address pages in physical memory for block allocation, then, a least recently used and most sparsely allocated page is identified and paged-out to the back-up store.

Abstract: A computer system is provided which enables automatic memory operations independently of a CPU. The computer system includes a virtual machine and a logical memory system which is accessed by the virtual machine through a binding register unit, enabling the virtual machine to allocate blocks and specify the length of the blocks. Data within the blocks can also be specified by the user by relative indexing with respect to a block specifier in the binding register unit. The logical memory system is controlled by a separate memory management unit which manages the physical memory of the system and which manages the memory to have the logical memory system appearance to the virtual machine.