Abstract: The graphics data processing apparatus which can logically combine the color data for two image arrays on a pixel by pixel basis, according to a nonlinear saturating function. Two examples of such functions are addition with saturation at the maximum value and subtraction with saturation at the minimum value. These functions can be employed to obtain computer graphics effects not feasible using other function, such as simulating spray painting and light mixing.

Abstract: A method of comparing two binary quantities, which includes comparing corresponding bits of each of the binary quantities and generating comparison signals to indicate equality and inequality of corresponding bits of the quantities. The comparison signals are transferred to a transfer line with the signals being arranged in order on the transfer line from the signal corresponding to the most significant bits to that corresponding to the least significant bits. A selected number of the comparison signals are coupled in order of priority from that corresponding to the most significant bits to that corresponding to the least significant bits, to an output EQUALS line in response to a plurality of decode signals.

Abstract: A single-level multiplexer (70) has a plurality of stages (72-78), one for each bit. In each stage, a select transistor (84) has a current path coupling an output node (86) to a common node (88), and a control element that is coupled to a select signal line (80). A data transistor (90) has a current path connecting a voltage supply (92) to the common node (88), and a control element connected to a data signal source (82). Common node (88) is connected to a current source (94, 96, 98, 100). The output node (86) of each stage is coupled together with the output nodes of the other states to an output (108) of the multiplexer.

Abstract: A method of reconditioning an electrically programmable semiconductor read only memory cell which includes heating the cell to a temperature which is sufficiently high and for a sufficient duration so that the Write/Erase window is re-opened.

Abstract: A dynamic random access memory cell array is disclosed which has storage capacitors and access transistors formed on the sidewalls of pillars created by trenches etched into the face of a semiconductor bar. A storage capacitor for a cell uses the sidewalls of the pillar as one plate and a polysilicon plug or web as the other plate. The channel of each access transistor is formed in the upper part of the sidewall of only a portion of the pillar, using an upper edge of the capacitor region as the source region of the transistor and having an N+ drain region at the top of the pillar. A cross-point array is made possible by merging two adjacent wordlines as a pair of overlying conductor strips extending along the face over the trenches, between pillars, and forming the transistor gates by alternate protrusions from these strips, extending down into the trenches at the channel area.

Abstract: A transient protection circuit comprising using a circuit connected to operate as a diode while presenting lower forward voltage drop for the same area and current as in pn junction diodes to provide greater efficiency. The circuit is a standard merged SCR circuit wherein a resistive path is provide between the base and collector of the pnp transistor and between the base and emitter of the npn transistor. In addition, there is provided a trip circuit wherein current is shunted away from the lateral transistor after a predetermined threshold current is passed through said transistor to minimize current drawn through the later transistor.

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: The specification discloses circuitry for compensating integrated circuits for negative internal ground voltage glitches. An output transistor (30) receives input signals at its base and has an emitter connected through a Schottky diode (32) to internal circuit ground. The compensation circuit includes a transistor (42) coupled to the base of transistor (30) and having an emitter also coupled to internal circuit ground. A capacitor (44) is connected between the base of transistor (42) and a source of bias voltage. Transistor (42) is rendered conductive by the occurrence of negative voltage glitches on the circuit ground, thus reducing voltage on the base of transistor (30) to prevent premature conduction by transistor (30).

Abstract: Metal interconnects and method for forming same such that an intermediately formed aluminum layer provides an etch stop and etch mask during the tungsten etch back. The method may be used to form tungsten contacts without requiring pre-metal planarization of the semiconductor body.

Abstract: A plasma dry etch process for etching deep trenches in single crystal silicon material with controlled wall profile, for trench capacitors or trench isolation structures. HCl is used as an etchant under RIE conditions with a SiO.sub.2 hard mask. The SiO.sub.2 hard mask is forward sputtered during the course of the Si etch so as to slowly deposit SiO.sub.x (x<2) on the sidewalls of the silicon trench. Since the sidewall deposit shadows etching at the bottom of the trench near the sidewall, the effect of this gradual buildup is to produce a positively sloped trench sidewall without "grooving" the bottom of the trench, and without linewidth loss. This process avoids the prior art problems of mask undercut, which generates voids during subsequent refill processing, and grooving at the bottom of the trench, which is exceedingly deleterious to thin capacitor dielectric integrity.

Abstract: A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

Abstract: The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

Abstract: An output load drive circuit including circuitry for adjusting a drive circuit bias current during operation in order to control driver circuit stability. The driver further includes circuitry which is self adjusting in response to ambient temperature fluctuations to control the overall gain of the driver.

Abstract: Disclosed is a proces for making a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

Abstract: A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrating resistor (64) and an integrating capacitor (68). The oscillator resistor (70) and integrator resistor (64) are designed such that their ratio will remain constant despite variations in actual value due to manufacturing inaccuracies. The oscillator capacitor (72) and integrating capacitor (68) are similarly designed. Consequently, an optimum peak integration value can be obtained at full scale input despite variations in actual resistive and capacitive values.

Abstract: A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme.

Abstract: A self contained circuit to enable a tank type (coil/capacitor) voltage controlled oscillator to start up and free run from a known state. The circuit allows the oscillator to be stopped to within two periods by invoking its only input logic signal and also restarted with no adverse effects on its free running operation. It includes three current mirrors, one which sets the current for the other two mirrors and of the final two, one actively sets a bias on a coil (stops oscillation) while the other makes up for the lack of coil bias by providing an equivalent amount current influx to the oscillator in the free running condition.

Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a quasi-folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects one of the two segments to be connected to one of the two bit lines. Instead of being interleaved one-for-one, the word lines for cells to be connected to the two bit lines are in groups one group for each segment line; the groups are interleaved. The combined segment line and bit line capacitance has a more favorable ratio to the storage capacitance, compared to the one-for-one interleaved layout.

Abstract: A bulk charge modulated transistor threshold sensing element (12) comprises a first region (18) having an enclosed structure, a gate region (24) that is preferably generally endless in shape, and a second region (26) to the interior of the gate region (24). The gate region (24) is doped and biased such that a potential well (100) is formed in the semiconductor substrate (11) a substantial distance from the surface thereof. When light (90) impinges on the element of the invention, carriers (94) collect in the potential well (100) in response thereto. The carriers (94) affect the threshold voltage of the transistor sensor element, and a threshold voltage differential is sensed as the sensing signal.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.