Abstract: The capacity of a single high-speed serial link between programmable logic devices or other integrated circuits may be provided using multiple lower-speed serial links arranged in parallel. Circuitry is provided for synchronizing and deskewing serial data streams from the multiple lower-speed serial links. At a receiving integrated circuit, a first-in-first-out buffer may be associated with each of the lower-speed serial links. Each first-in-first-out buffer may be used to provide both synchronization functions and channel alignment functions.

Abstract: Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

Abstract: A system is provided that uses identity-based encryption to support secure communications. Messages from a sender to a receiver may be encrypted using the receiver's identity and public parameters that have been generated by a private key generator associated with the receiver. The private key generator associated with the receiver generates a private key for the receiver. The encrypted message may be decrypted by the receiver using the receiver's private key. The system may have multiple private key generators, each with a separate set of public parameters. Directory services may be used to provide a sender that is associated with one private key generator with appropriate public parameters to use when encrypting messages for a receiver that is associated with a different private key generator. A certification authority may be used to sign directory entries for the directory service. A clearinghouse may be used to avoid duplicative directory entries.

Abstract: A system is provided that allows users to communicate securely. A key management service may generate a single public-key/private-key pair. A sender who desires to send a secure message to a receiver may encrypt the message using a message key. The sender may use the public key to encrypt the message key and policy information that dictates how the message may be accessed. The receiver may pass the public-key-encrypted message key and policy information to the key management service. The key management service decrypts this information using the private key. After the key management service uses the policy information to verify that the receiver is authorized to access the message, the key management service may provide the decrypted message key to the receiver. The receiver may use this unencrypted version of the message key to decrypt the message-key-encrypted message from the sender.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

Abstract: Methods and apparatus are provided for conveying configuration data to a programmable logic device integrated circuit. When the configuration data is loaded into configuration memory on the programmable logic device integrated circuit, the programmable logic device integrated circuit performs custom logic functions. The programmable logic device integrated circuit or an associated configuration device integrated circuit may be provided with power conversion circuitry and transceiver circuitry. The power conversion circuitry converts received radio-frequency signals into power. The power from the power conversion circuitry is provided to the transceiver, loading, and configuration memory circuitry. The transceiver circuitry is connected to an antenna that receives wirelessly-transmitted configuration data and is used to transmit confirmation messages following successful loading of the configuration data into the configuration memory.

Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.

Abstract: A programmable logic device test generation tool is provided that produces test configuration data and test vectors for testing programmable logic device integrated circuits. A graph generation tool converts a netlist or other circuit description of a programmable logic device integrated circuit into a graph having nodes and edges. A timing analysis tool may be used to help produce test constraints. Based on the test constraints, an automatic test generator processes the graph to produce the test configuration data and test vectors. In processing the graph with the automatic test generator, the graph may be divided into multiple testable subgraphs. Each subgraph may be processed using an iterative approach in which a cost function threshold is adjusted in a number of steps until a target test coverage is obtained or processing saturates.