Abstract: Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.

Abstract: Broadband antennas and handheld electronic devices with broadband antennas are provided. A handheld electronic device may have a housing in which electrical components such as integrated circuits and a broadband antenna are mounted. The broadband antenna may have a ground element and a resonating element. The resonating element may have two arms of unequal length and may have a self-resonant element. The antenna may have a feed terminal connected to the self-resonant element and a ground terminal connected to the ground element. The self-resonant element may be near-field coupled to one of the arms of the resonating element. With one suitable arrangement, the self-resonant element may be formed using a conductive rectangular element that is not electrically shorted to the ground element or the arms of the resonating element. The antenna may operate over first and second frequency ranges of interest.

Abstract: Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.

Abstract: Systems and methods for secure messaging are provided. A sender may encrypt an email message for a recipient. The email message may contain authenticated sender-recipient mapping information. When a recipient requests a client software download or private key from a service provider, the service provider can verify the authenticity of the sender-recipient mapping information. This assures the service provider that the recipient has received a communication from the sender and allows the service provider to provide services to the recipient based on the status of the sender. If the sender is a member of an organization that is a direct customer of the service provider, the service provider may satisfy the recipient's service request.

Abstract: An encoder is provided for converting thermometer code data with bubbles to binary format. An integrated circuit may have circuitry such as digital phase-locked loop circuitry. A thermometer code data word may be used as a control signal for the circuitry. It may be desirable to monitor the thermometer code data word for testing or for downstream processing by control logic on the integrated circuit. The encoder performs thermometer code to binary encoding without requiring that the thermometer code be error corrected to remove bubbles. A bubble detection circuit may be used to detect when the thermometer code data contains bubbles. The encoder may use carry look-ahead adders and pipeline stages.

Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

Abstract: An integrated circuit is provided with adjustable transistor body bias circuitry and adjustable power supply circuitry. The adjustable circuitry may be used to selectively apply body bias voltages and power supply voltages to blocks of programmable logic, memory blocks, and other circuit blocks on the integrated circuit. The body bias voltages and power supply voltages may be identified by computer aided design tools. The body bias voltages may be used to reduce leakage currents and power consumption when high speed circuit block operation is not required. Reduced power supply voltages may also be used to reduce power consumption when high speed circuit block operation is not required. To ensure optimum switching speeds, circuit blocks for which high-speed performance is critical can be provided with minimal body bias voltage or no body bias and can be provided with maximum power supply levels.

Abstract: A compact tunable antenna for a handheld electronic device and methods for calibrating and using compact tunable antennas are provided. The antenna can have multiple ports. Each port can have an associated feed and ground. The antenna design can be implemented with a small footprint while covering a large bandwidth. The antenna can have a radiating element formed from a conductive structure such as a patch or helix. The antenna can be shaped to accommodate buttons and other components in the handheld device. The antenna may be connected to a printed circuit board in the handheld device using springs, pogo pins, and other suitable connecting structures. Radio-frequency switches and passive components such as duplexers and diplexers may be used to couple radio-frequency transceiver circuitry to the different feeds of the antenna. Antenna efficiency can be enhanced by avoiding the use of capacitive loading for antenna tuning.

Abstract: Computer-aided design tools analyze a custom logic design for a programmable logic device integrated circuit. The tools identify distinct clock domains in the design. The tools also identify which of the clock domains are synchronous. The tools examine the synchronous clock domains to determine which of the clock domains have required fixed phase relationships. Clocks for clock domains that do not have required fixed relationships can be adjusted in phase to minimize power supply simultaneous switching noise. Noise may be minimized by making clock phase adjustments using a programmable phase-locked loop circuit.

Abstract: Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.

Abstract: Programmable logic device integrated circuits are provided that have configurable receivers with dynamic phase alignment capabilities. In situations in which receivers require dynamic phase alignment circuitry, programmable logic elements can be configured to implement a dynamic phase alignment data capture and synchronization circuit. In situations in which dynamic phase alignment receiver circuitry is not required, resources are made available for implementing other user logic. Multiple dynamic phase alignment receiver circuits can share an eight-phase dynamic phase alignment clock signal that is generated by a phase-locked-loop circuit. Switches may be configured to selectively route the dynamic phase alignment clock signal to desired locations on the programmable logic device integrated circuit.

Abstract: Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to produce configuration data containing alternative configuration memory settings each of which is optimized for programmable logic devices with different performance characteristics. During manufacturing, programmable logic devices are tested to identify their performance characteristics. A bin code is stored in non-volatile memory in each device to specify which performance characteristics are associated with that device. During programming, the bin code of a given device is used to decide which of the alternative configuration memory settings are to be discarded. The retained subset of the configuration data is loaded into configuration memory in the given device.

Abstract: The various embodiments disclose capacitor multiplier circuits that may be integrated into imaging devices, such as for semiconductor Complimentary Metal Oxide Semiconductor (CMOS) image sensors, to create an effective capacitance in response to a low frequency, such as row-wise temporal noise, that may be generated along a row of image sensor pixels. The created effective capacitance from any one of the capacitor multiplier circuits along with a small signal resistance created by a trans-conductance of a current biasing transistor form a low pass filter that will attenuate the low frequency noise.

Abstract: Methods, methods of making, devices, and systems for image sensors that include isolation regions are disclosed. A semiconductor imager includes a pixel array and peripheral circuitry arranged on at least one side of the pixel array. Array devices are formed as part of the pixel array and periphery devices are formed in the periphery. Array isolation regions are disposed around at least a portion of at least some of the array devices and periphery isolation regions are disposed around at least a portion of at least some of the periphery devices. Within the semiconductor imager, the periphery isolation regions are configured differently from the array isolation regions. The semiconductor image sensor may be included in as part of an imaging system that includes a processor.

Abstract: An imager pixel and imaging device and system including an imager pixel for discharging a floating diffusion region are described. The imager pixel includes a photoconversion regions floating diffusion region, and a reset diode. A reset diode is coupled to the floating diffusion region and, when activated, discharges accumulated and collected charge from the photoconversion and the floating diffusion regions. Following successive accumulation, transfer and collection processes, the reset diode again discharges residual accumulated and collected charge from the photoconversion and the floating diffusion regions.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays that may be configured for true dual port operation or simple dual port operation. The memory arrays include memory cells arranged in rows and columns and associated row address lines and data lines. Sense amplifiers and write drivers are used for reading and writing data. Precharge drivers are used to precharge the data lines prior to read operations. Configurable multiplexer circuitry in the array has read paths through which data is provided to the sense amplifiers from the memory cells. The multiplexer circuitry has write paths through which data from the write drivers is written into the memory cells. The read paths and the write paths contain no more than a single pass gate each. Each precharge driver may be connected to a respective one of the data lines with no intervening pass gates.

Abstract: Antennas, handheld electronic devices containing antennas, and methods for using antennas and handheld electronic devices are provided. A handheld device may have a conductive case. The antenna can be formed as part of a button such as a pushbutton. The pushbutton may protrude from the conductive case sufficiently to allow good transmission and reception of wireless signals. The protruding antenna contains a radiating element, while the conductive case serves as a ground. The radiating element may be formed from a low-profile antenna structure such as a planar antenna structure formed on a circuit board substrate. The pushbutton may be used to control operation of the handheld electronic device. With one suitable arrangement, actuation of the pushbutton antenna causes the antenna to protrude from the case and turns on transceiver circuitry in the handheld device.

Abstract: An integrated circuit is provided that has circuitry containing metal-oxide-semiconductor transistors with body terminals. The body terminals may be biased with an externally supplied body bias voltage that reduces power consumption. During power-up operations, the external body bias voltage may temporarily not be available. In this situation, boost circuitry may produce an internal power supply signal that may be used in place of the unavailable external body bias voltage, thereby reducing leakage currents and power consumption during power up. A multiplexer may be used in routing an appropriate body bias signal to the transistors. The boost circuitry and multiplexer may be controlled by control signals that are generated by control logic. The control logic may produce the control signals by monitoring external and internally generated power supply voltage levels during power up operations.

Abstract: Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals.

Abstract: Voltage regulator circuitry is provided that exhibits a high power supply rejection ratio and a wide output voltage range. The voltage regulator circuitry can regulate power supply voltages for circuitry on a programmable logic device such as transistor body bias circuitry and configuration random-access-memory array circuitry. The voltage regulator circuitry includes an n-channel metal-oxide-semiconductor drive transistor that is coupled between a power supply voltage terminal and an output terminal. The n-channel metal-oxide-semiconductor drive transistor has a gate that receives a control signal from an operational amplifier. A boost circuit generates an elevated power supply voltage for the operational amplifier. A programmable voltage divider is coupled to the voltage regulator's output. The operational amplifier produces the control signal by comparing a feedback signal from the voltage divider to a reference voltage.