Abstract: A handheld electronic device is provided that contain wireless communications circuitry. The wireless communications circuitry may include antenna structures. A first antenna may handle first and second communications bands. A second antenna may handle additional communications bands. The first and second antennas may be located at opposite ends of the handheld electronic device. Conductive structures in the handheld electronic device may form an antenna ground plane. The antenna ground plane may have portions defining an antenna slot. An L-shaped antenna resonating element may be located adjacent to the slot. In the first communications band, the L-shaped antenna resonating element may serve as a non-radiating coupling stub that excites the antenna slot. In the second communications band, the L-shaped antenna resonating element may transmit and receive radio-frequency signals.

Abstract: Hybrid circuits for electronic devices and accessories for electronic devices are provided. One or more pairs of hybrid circuits may convey audio signals, noise cancellation audio signals, microphone signals, control signals, and other signals between an electronic device and an accessory. The hybrid circuits may include a voltage controlled current source, a differential amplifier, separate signal and ground pins, multiple ground lines, an amplifier on a ground noise sense input line that can sense ground noise that may result from parasitic resistance, and other circuitry.

Abstract: A URL verification service is provided that is used to evaluate the trustworthiness of universal resource locators (URLs). As a user browses the world wide web, the URL for a web page to which the user is browsing is captured by the service. The URL has a second level domain corresponding to a web site. The URL verification service identifies a proposed brand that should be associated with the URL if the URL is trustworthy. The proposed brand and the second level domain are used as database queries to query a database such as a search engine database. The results of the database query are processed to determine whether the URL is legitimately associated with the URL. To ensure that the proposed brand is identified accurately, the URL verification service gathers brand information using web page content, secure sockets layer certificate content, or other web site attributes.

Abstract: Memory elements for integrated circuit are provided that have efficient transistor layouts. The integrated circuits may be programmable logic device integrated circuits on which memory elements are formed into arrays. Each memory element may have a pair of cross-coupled inverters, an address transistor, and a clear transistor. The transistors in each memory element may be formed from n-type and p-type semiconductor regions that are crossed by only three gate conductor fingers. Programmable transistors on the integrated circuit may be controlled by static output signals from the memory elements. The programmable transistors may be used to form multiplexers. The multiplexers may be formed from n-type regions that are crossed by only three gate fingers each. The gate fingers of the multiplexers may be aligned with the gate fingers of the transistor structures of the memory elements.

Abstract: Broadband antennas and handheld electronic devices with broadband antennas are provided. A handheld electronic device has integrated circuits, a display, and a battery mounted within a housing. The housing has a planar inner surface. A broadband antenna for the handheld electronic device has a ground element and a resonating element. The ground element and resonating element may have the same shape and may have the same size. The ground element and resonating element may lie in a common plane and be separated by a gap that lies in the common plane. The plane in which the ground element and resonating element lie may be parallel to the planar inner surface of the housing. Electronic components such as the integrated circuits, display, and battery can be mounted in the handheld device so that they do not overlap the gap between the ground element and the resonating element.

Abstract: A system is provided that uses identity-based encryption (IBE) to support secure communications. Messages from a sender may be encrypted using an IBE public key and IBE public parameter information associated with a recipient. The recipient may decrypt IBE-encrypted messages from the sender using an IBE private key. A host having a service name may be used to store the IBE public parameter information. The sender may use a service name generation rule to generate the service name based on the IBE public key of the recipient. The sender may use the service name to obtain the IBE public parameter information from the host.

Abstract: Methods and apparatus for transferring patients are provided. A patient transfer device may have a wheeled base and a lateral transfer structure. A patient may lie supine on a patient support structure on top of a transfer sheet. Airbags may be adjusted beneath the transfer sheet to form channels. To transfer the patient from the patient support structure to the wheeled base, the lateral transfer structure is extended into the channels beneath the patient. A stretcher frame is formed from the extended lateral transfer structure. A stretcher that supports the patient is formed by attaching the transfer sheet to the stretcher frame. After the stretcher has been formed, the extended portions of the lateral transfer structure may be retracted to move the stretcher and patient on top of the wheeled base. The patient transfer device may be adjusted to allow the patient to assume a sitting position during transit.

Abstract: Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a redundancy control signal. During manufacturing, the integrated circuitry may be tested. If a defect is identified on the integrated circuit, the redundancy control signal may be used in switching redundant circuitry into place bypassing the defect. The integrated circuit may contain an array of logic regions. Each logic region may contain adders and multiplexer circuitry for selectively combining the multiplexers to form larger adders. The multiplexer circuitry in each logic region may be controlled by propagate signals from the adders and by static redundancy control signals.

Abstract: Integrated circuit bond pads are provided for forming wire bonds to integrated circuit package pins. Each pad uses a bond pad structure that provides room for under-pad circuitry. The under-pad circuitry can be connected to other circuitry on the integrated circuit, thereby providing efficient use of circuit real estate. The bond pad structures are formed in the dielectric stack portion of the integrated circuit using dummy bond pads and bond pad support structures. Bond pad support structures may be formed from metal in metal interconnect layers. Vias may be used to connect the bond pad support structures to each other and to the dummy bond pads. Bond pad support structures may be formed in a polysilicon layer at the bottom of the dielectric stack. A contact layer contains metal plugs that connect the polysilicon bond pad support structures to the lowermost metal-layer bond pad support structures.

Abstract: A camera system uses a highly sensitive camera such as an intensified charge-coupled-device camera to acquire images. An image acquisition and processing tool can place the camera in a low-sensitivity mode and a high-sensitivity mode. In the low-sensitivity mode, a reference image may be acquired of a target that is illuminated by a light-emitting-diode. In the high sensitivity mode, low-photon-flux image data frames are acquired using a charge-coupled-device image sensor in the camera. The image acquisition and processing tool displays the acquired image data frames on top of the reference image in real time, so that a user is provided with immediate visual feedback. The image acquisition and processing tool has image preprocessing filters for enhancing image quality such as a sensor noise threshold filter, a cosmic ray filter, and a photon shape optimization filter. Pipeline filters may be used to further process acquired image data frames.

Abstract: Voltage regulator circuitry is provided. The voltage regulator circuitry may contain a drive transistor that is controlled by the output of an operational amplifier. The drive transistor may supply a regulated voltage to a load. The operational amplifier may compare a reference voltage and a feedback signal at its inputs. The operational amplifier may include first and second stages. An adjustable resistor may be provided between the first and second stages. Control circuitry may control the resistance of the adjustable resistor based on the amount of current flowing through the load to ensure stable operation of the voltage regulator circuitry. Overshoot and undershoot detection and compensation circuitry may compensate for overshoot and undershoot in the regulated voltage. Voltage ramp control circuitry may be used to control the ramp rate of the regulated voltage.

Abstract: The present invention provides systems and methods for dynamic detection and prevention of electronic fraud and network intrusion using an integrated set of intelligent technologies. The intelligent technologies include neural networks, multi-agents, data mining, case-based reasoning, rule-based reasoning, fuzzy logic, constraint programming, and genetic algorithms. The systems and methods of the present invention involve a fraud detection and prevention model that successfully detects and prevents electronic fraud and network intrusion in real-time. The model is not sensitive to known or unknown different types of fraud or network intrusion attacks, and can be used to detect and prevent fraud and network intrusion across multiple networks and industries.

Abstract: Integrated circuits compliant with a serial communications protocol with optional features are provided. The optional features include control plane features such as flow control, retry-on-error, clock tolerance compensation, and idle codes and include data path features such as streaming and packetized data modes, configurable data ports and user-defined data channel multiplexing. An integrated circuit compliant with the protocol can transmit streaming data with or without clock tolerance compensation codes. A priority data port can be used to implement retry-on-error functions while user-defined data channels carry user data. The data ports can be individually configured to perform different levels of cyclic redundancy checking. Logic design tools are used to create compliant circuits and systems.

Abstract: Adjustable transceiver circuitry is provided for programmable integrated circuits such as programmable logic device integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The dynamic phase alignment circuit contains a bypassable synchronizer. Four modes of operation are supported by the transceiver circuitry including a normal source synchronous mode, a normal dynamic phase alignment mode, a soft clock data recovery mode, and a phase-locked-loop source synchronous mode. In normal source synchronous mode, the dynamic phase alignment circuit performs no phase alignment or clock rate matching. In normal dynamic phase alignment mode, the dynamic phase alignment circuit performs only phase alignment operations. In soft clock data recovery mode, programmable logic on the programmable integrated circuit is configured to perform rate matching and phase alignment.

Abstract: Power regulator circuitry is provided for powering loads such as memory element arrays on integrated circuits. The power regulator circuitry may have a regulated power supply circuit and a switch-based power supply circuit. Control circuitry can control the regulated power supply circuit and the switch-based power supply circuit. The control circuitry may include a power supply power-on-reset control circuit. The power supply power-on-reset control circuit may receive a system power-on-reset control signal from a system power-on-reset control circuit. Based on the system power-on-reset control signal and monitored power supply voltages, the power supply power-on-reset control circuit may apply power-on-reset control signals to depletion mode transistors in the power regulator circuitry to ensure that nodes within the power regulator circuitry have defined values during power-up operations.

Abstract: An antenna may be formed from conductive regions that define a gap that is bridged by shunt inductors. The inductors may have equal inductances and may be located equidistant from each other to form a scatter-type antenna structure. The inductors may also have unequal inductances and may be located along the length of the gap with unequal inductor-to-inductor spacings, thereby creating a decreasing shunt inductance at increasing distances from a feed for the antenna. This type of antenna structure functions as a horn-type antenna. One or more scatter-type antenna structures may be cascaded to form a multiband antenna. Antenna gaps may be formed in conductive device housings.

Abstract: Systems and methods are provided for avoiding memory address conflicts in systems containing shared memory. Upon system power up, programmable logic device integrated circuits, microprocessors, and other integrated circuits with processing capabilities are provided with unique initialization data memory addresses. Each unique initialization data memory address corresponds to a respective non-overlapping block of memory in the shared memory. During initialization operations, the integrated circuits retrieve initialization data from the shared memory using the unique initialization data memory addresses. The integrated circuits can be organized using a master-slave architecture. The master can load the initialization data memory addresses into the slave integrated circuits using communications circuitry that is active after the slaves have powered up but before the slaves have been initialized.

Abstract: A URL verification service is provided that is used to evaluate the trustworthiness of universal resource locators (URLs). As a user browses the world wide web, a URL verification client captures a URL associated with a web page of unknown authenticity. The URL verification client transmits the captured URL to a URL verification server. The URL verification server compares the URL to actively maintained whitelist and blacklist information. The server also uses the URL and a user-supplied or automatically-extracted brand to query a search engine. The URL verification server processes the response of the search engine to the search engine queries and the results of cache and whitelist and blacklist comparisons to determine whether the captured URL is legitimately associated with the brand. The results of the URL evaluation process are transmitted from the URL verification server to the URL verification client, which notifies user.

Abstract: Systems and methods for secure messaging are provided. A sender may encrypt content and send the encrypted content to a recipient over a communications network. The encrypted content may be decrypted for the recipient using a remote decryption service. Encrypted message content may be placed into a markup language form. Encrypted content may be incorporated into the form as a hidden form element. Form elements for collecting recipient credential information such as username and password information may also be incorporated into the form. At the recipient, the recipient may use the form to provide recipient credential information to the remote decryption service. The recipient may also use the form to upload the encrypted content from the form to the decryption service. The decryption service may provide the recipient with access to a decrypted version of the uploaded content over the communications network.

Abstract: Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.