Patents Represented by Attorney Treyz Law Group
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Patent number: 7634713Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.Type: GrantFiled: May 16, 2006Date of Patent: December 15, 2009Assignee: Altera CorporationInventor: Ninh D. Ngo
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Patent number: 7634085Abstract: Systems and methods for supporting an identity-based-encryption (IBE) scheme with partial attribute matching capabilities are provided. Plaintext may be encrypted into ciphertext using an IBE public key that is based on an attribute set w. A recipient of the ciphertext may have the attributes in an overlapping but different attribute set w?. The recipient may request an IBE private key for decrypting the ciphertext from an IBE private key generator. After verifying the recipient's credentials, the IBE private key generator may generate IBE private key components based on the recipient's attribute set w?. The recipient may use an IBE private key SK constructed from the IBE private key components to decrypt the ciphertext. Decryption will be successful even though attribute set w? is different from attribute set w, provided that the overlap |w?w?| is greater than a threshold value.Type: GrantFiled: March 25, 2005Date of Patent: December 15, 2009Assignee: Voltage Security, Inc.Inventors: Amit Sahai, Brent R. Waters
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Patent number: 7629831Abstract: Booster circuitry is provided that contains capacitor protection circuitry. The booster circuitry receives a digital input signal on an input line and provides a corresponding boosted digital output signal on an output line. The digital input signal may be received from an oscillator. The digital output signal may be a clock that is applied to a charge pump on a programmable logic device integrated circuit. The booster circuitry contains a metal-oxide-semiconductor capacitor. The capacitor protection circuitry ensures that the voltage across the capacitor in the booster circuit remains above a desired minimum voltage and below a desired maximum voltage during operation. The capacitor protection circuitry includes a control circuit that monitors the capacitor voltage when the booster circuit is operated while the oscillator is off and transistor-based circuitry that discharges one of the capacitor's terminals to a predetermined level when the booster circuit is operated while the oscillator is on.Type: GrantFiled: October 11, 2006Date of Patent: December 8, 2009Assignee: Altera CorporationInventors: Srinivas Perisetty, Jeffery Chow
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Patent number: 7627128Abstract: Electronic devices and accessories such as headsets for electronic devices are provided. A microphone may be included in an accessory to capture sound for an associated electronic device. Buttons and other user interfaces may be included in the accessories. An accessory may have an audio plug that connects to a mating audio jack in an electronic device, thereby establishing a wired communications link between the accessory and the electronic device. The electronic device may include power supply circuitry for applying bias voltages to the accessory. The bias voltages may bias a microphone and may adjust settings in the accessory such as settings related to operating modes. User input information may be conveyed between the accessory and the electronic device using ultrasonic tone transmission. The electronic device may also gather input from the accessory using a voltage detector coupled to lines in the communications path.Type: GrantFiled: September 3, 2008Date of Patent: December 1, 2009Assignee: Apple Inc.Inventors: Wendell B. Sander, Jeffrey Terlizzi, Douglas M. Farrar
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Patent number: 7623077Abstract: Compact portable wireless devices and antennas for compact portable wireless devices are provided. The compact portable wireless device may be part of a piece of sports equipment. A compact portable wireless device may include a transceiver module that is used in communicating with equipment such as a handheld electronic device. An antenna for a compact portable wireless device can have a relatively small size while exhibiting high efficiency. A planar ground structure for the antenna may be formed from a circuit board on which integrated circuits have been mounted. A curved inverted-F resonating element may be attached to the ground structure. A battery may be provided to power the compact portable wireless device. The battery may be used as a parasitic antenna element.Type: GrantFiled: December 15, 2006Date of Patent: November 24, 2009Assignee: Apple Inc.Inventors: Shu-Li Wang, Juan Zavala, Christopher David Prest
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Patent number: 7623078Abstract: Antennas are provided for portable electronic devices. A portable electronic device may have a port that receives a wireless communications adapter. The adapter may be used to provide wireless functionality for the portable electronic device. The adapter may contain a chip antenna that serves as an antenna resonating element. A printed circuit board within the adapter may contain conductor that has been patterned to form a ground plane for the antenna. The portable electronic device may have a conductive structure such as a housing portion. The conductive structure of the portable electronic device serves as a parasitic antenna element that improves antenna efficiency. The portable electronic device may be a handheld electronic device with music player functionality that communicates with a compact portable wireless device in a piece of sports equipment.Type: GrantFiled: December 15, 2006Date of Patent: November 24, 2009Assignee: Apple Inc.Inventor: Shu-Li Wang
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Patent number: 7624269Abstract: Secure messages may be sent between senders and recipients using symmetric message keys. The symmetric message keys may be derived from a master key using a key generator at an organization. A gateway may encrypt outgoing message using the derived keys. Senders in the organization can send messages to recipients who are customers of the organization. The recipients can authenticate to a decryption server in the organization using preestablished credentials. The recipients can be provided with copies of the derived keys for decrypting the encrypted messages. A hierarchical architecture may be used in which a super master key generator at the organization derives master keys for delegated key generators in different units of the organization. An organization may have a policy server that generates non-customer symmetric message keys. The non-customer symmetric message keys may be used to encrypt messages sent by a non-customer sender to a recipient at the organization.Type: GrantFiled: July 9, 2004Date of Patent: November 24, 2009Assignee: Voltage Security, Inc.Inventors: Guido Appenzeller, Xavier Boyen, Terence Spies
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Patent number: 7620853Abstract: Integrated circuits such as programmable logic device integrated circuits have configuration random-access memory elements. The configuration random-access memory elements are tested to determine whether any of the elements have resistive bridging faults at their outputs. During testing, a pattern of test configuration data is loaded into the configuration random-access memory elements. The programmable logic device is placed in user mode to clear programmable logic registers on the device. The configuration random-access memory elements are sensitized to the presence of resistive bridging faults by performing read operations. After sensitizing the configuration random-access memory elements, a tester applies test vectors to the programmable logic of the programmable logic device. As the test vectors are applied, the tester observes whether the programmable logic of the device is performing properly or has been affected by the presence of a resistive bridging fault.Type: GrantFiled: March 5, 2007Date of Patent: November 17, 2009Assignee: Altera CorporationInventors: Zunhang Yu Kasnavi, Eng Ling Ho
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Patent number: 7612725Abstract: A handheld electronic device may be provided that contains wireless communications circuitry. The handheld electronic device may have a housing and a display. The display may be attached to the housing a conductive bezel. The handheld electronic device may have one or more antennas for supporting wireless communications. A ground plane in the handheld electronic device may serve as ground for one or more of the antennas. The ground plane and bezel may define a opening. A rectangular slot antenna or other suitable slot antenna may be formed from or within the opening. One or more antenna resonating elements may be formed above the slot. An electrical switch that bridges the slot may be used to modify the perimeter of the slot so as to tune the communications bands of the handheld electronic device.Type: GrantFiled: June 21, 2007Date of Patent: November 3, 2009Assignee: Apple Inc.Inventors: Robert J. Hill, Robert W. Schlub, Ruben Caballero
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Patent number: 7606684Abstract: A model creation tool is provided that automatically evaluates potential econometric models and, given a set of historical data on which the model is intended to operate and other constraints, automatically identifies an optimum model. The optimum model may be an autoregressive model. The optimum model is defined by a set of optimum model parameters and optimum model coefficients. The optimum model parameters may include a model order such as an autoregressive model order, a seasonality function parameter, a trend function parameter, and a parameter that sets a tolerance that is used when performing principal components dimension reduction operations on the historical data.Type: GrantFiled: December 8, 2005Date of Patent: October 20, 2009Assignee: SignalDemand, Inc.Inventor: Robert D. Pierce
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Patent number: 7595759Abstract: Handheld electronic devices are provided that contain wireless communications circuitry having at least first and second antennas. An antenna isolation element reduces signal interference between the antennas, so that the antennas may be used in close proximity to each other. A planar ground element may be used as a ground by the first and second antennas. The first antenna may be formed using a hybrid planar-inverted-F and slot arrangement in which a planar resonating element is located above a rectangular slot in the planar ground element. The second antenna may be formed from an L-shaped strip. The planar resonating element of the first antenna may have first and second arms. The first arm may resonate at a common frequency with the second antenna and may serve as the isolation element. The second arm may resonate at approximately the same frequency as the slot portion of the hybrid antenna.Type: GrantFiled: January 4, 2007Date of Patent: September 29, 2009Assignee: Apple Inc.Inventors: Robert W. Schlub, Robert J. Hill, Juan Zavala, Ruben Caballero
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Patent number: 7592832Abstract: An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals to minimize power consumption. The adjustable body bias circuitry can be controlled using programmable elements on the integrated circuit that are loaded with configuration data. The integrated circuit may be a programmable logic device integrated circuit containing programmable logic. The adjustable body bias circuitry can produce an adjustable negative body bias voltage for biasing n-channel metal-oxide-semiconductor transistors. The adjustable body bias circuitry contains a bandgap reference circuit, a charge pump circuit, and an adjustable voltage regulator.Type: GrantFiled: June 27, 2008Date of Patent: September 22, 2009Assignee: Altera CorporationInventor: Srinivas Perisetty
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Patent number: 7590211Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have resource-efficient receiver circuitry. In source-synchronous system environments, an integrated circuit receives data on multiple buses, each of which has a reference clock signal and associated data signals. One of the reference clocks is provided to a phase-locked-loop circuit, which generates a serial clock and parallel clock for capturing and deserializing data for one of the buses. Each additional bus has an associated phase detector and delay-locked loop in place of a phase-locked loop. The phase detector and delay-locked loop in each additional bus shift the serial clock from the phase-locked loop to produce a serial clock for the additional bus. A parallel clock for each additional bus may be produced using a divider.Type: GrantFiled: July 17, 2006Date of Patent: September 15, 2009Assignee: Altera CorporationInventor: Ali Burney
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Patent number: 7590236Abstract: Systems and methods for supporting symmetric-bilinear-map and asymmetric-bilinear-map identity-based-encryption (IBE) key exchange and encryption schemes are provided. IBE key exchange schemes use an IBE encapsulation engine to produce a secret key and an encapsulated version of the secret key. An IBE unencapsulation engine is used to unencapsulate the encapsulated key. IBE encryption schemes use an IBE encryption engine to produce ciphertext from plaintext. An IBE decryption engine is used to decrypt the ciphertext to reveal the plaintext. The IBE unencapsulation engine and decryption engines use bilinear maps. The IBE encapsulation and encryption engines perform group multiplication operations without using bilinear maps, improving efficiency. IBE private keys for use in decryption and unencapsulation operations may be generated using a distributed key arrangement in which each IBE private key is assembled from private key shares.Type: GrantFiled: March 25, 2005Date of Patent: September 15, 2009Assignees: Voltage Security, Inc., The Board of Trustees of the Leland Stanford Junior UniversityInventors: Dan Boneh, Xavier Boyen
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Patent number: 7589584Abstract: Voltage regulator circuitry is provided. The voltage regulator circuitry is suitable for powering core logic on a programmable logic device. The voltage regulator circuitry receives an external power supply voltage and reduces the external power supply voltage to a core power supply voltage if needed. If the external power supply voltage is at the same level needed to power the core logic, the voltage regulator circuitry passes the power supply voltage to the core logic. The voltage regulator circuitry monitors the core power supply voltage using a feedback path. Overshoot and undershoot fluctuations are minimized. The external power supply voltage may be supplied to a first bus. The core power supply voltage may be distributed on a second bus. A ring of transistors may be used to convey power from the first bus to the second bus. Control circuitry may control the ring of transistors based on programmable setpoint voltages.Type: GrantFiled: April 1, 2005Date of Patent: September 15, 2009Assignee: Altera CorporationInventor: John Bui
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Patent number: 7589552Abstract: Integrated circuits such as programmable logic devices are provided that have circuit blocks such as memory blocks. The integrated circuits may be tested to determine whether the circuit blocks contain defects. If defective circuitry is identified, switching circuitry in the circuit blocks can be configured to switch redundant circuitry into use. Repairs may be made by loading repair data into fuses on the integrated circuit. Each circuit block may have an associated control circuit with a unique address. A master block repair controller may be used to route repair data to each control circuit over a shared bus using the unique addresses of the control circuits. Each control circuit may have register circuitry into which addresses and repair data are loaded. Testing circuitry may be used to supply test signals. Multiplexing circuitry can selectively route either the test signals or repair data to the control circuits over the shared bus.Type: GrantFiled: October 23, 2007Date of Patent: September 15, 2009Assignee: Altera CorporationInventors: Mario E. Guzman, Christopher F. Lane
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Patent number: 7587537Abstract: Input-output circuitry for integrated circuits such as programmable logic device integrated circuits is provided. The input-output circuitry can be configured to operate in a single-ended data mode or a serializer-deserializer mode using programmable routing circuitry such as programmable multiplexers. In single-ended data mode, data registers in the single-ended input-output circuitry may be used to handle transmitted and received single-ended data. In serializer-deserializer mode, the data registers may be configured to form a shift register. The shift register may be used in a serializer-deserializer circuit. Parallel-to-serial and serial-to-parallel data conversion operations may be performed using the shift register. The serializer-deserializer circuit may be connected to differential input-output circuitry such as a differential transmitter circuit or a differential receiver circuit. The data registers may be configured to operate as positive-edge-triggered or negative-edge-triggered devices.Type: GrantFiled: November 30, 2007Date of Patent: September 8, 2009Assignee: Altera CorporationInventor: Ali Burney
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Patent number: 7583103Abstract: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.Type: GrantFiled: March 30, 2007Date of Patent: September 1, 2009Assignee: Altera CorporationInventors: David Lewis, David Cashman
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Patent number: 7580521Abstract: A system is provided that uses identity-based encryption (IBE) to allow a sender to securely convey information in a message to a recipient over a communications network. IBE public key information may be used to encrypt messages and corresponding IBE private key information may be used to decrypt messages. Information on which IBE public key information was used in encrypting a given message may be provided to the message recipient with the message. Multiple IBE public keys may be used to encrypt a single message. A less sensitive IBE public key may be used to encrypt a more sensitive public key, so that the more sensitive public key can remain hidden as it is sent to the recipient.Type: GrantFiled: June 25, 2003Date of Patent: August 25, 2009Assignee: Voltage Security, Inc.Inventors: Terence Spies, Rishi R. Kacker, Guido Appenzeller, Matthew J. Pauker
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Patent number: 7571413Abstract: A programmable integrated circuit has multiple power supply voltages. Power supply voltages are distributed using power supply distribution lines. The integrated circuit has programmable power supply voltage selection switches. Each power supply voltage selection switch has its inputs connected to the power supply distribution lines and supplies a selected power supply voltage to a circuit block at its output. Test circuits are provided for testing the power supply voltage selection switches. During testing, the power supply voltage selection switches are adjusted to produce various power supply voltages at their outputs. The test circuit associated with each switch performs voltage comparisons to determine whether the switch is functioning properly. Each test circuit produces a test result based on its voltage comparison. The test results from the test circuits are provided to a scan chain, which unloads the test results from the integrated circuit to a tester for analysis.Type: GrantFiled: June 28, 2006Date of Patent: August 4, 2009Assignee: Altera CorporationInventors: Jayabrata Ghosh Dastidar, Srinivas Perisetty, Andy L. Lee