Patents Represented by Attorney Trop, Pruner & Hu, P.C.
  • Patent number: 8248862
    Abstract: The threshold voltage range of a multilevel memory cell may be increased without using a negative voltage pump. In one embodiment, an added positive voltage may be applied to the source of the selected cell. A boost voltage may be applied to the output of a sense amplifier. Non-ideal characteristics of a buffer that supplies the voltage to the selected cell may be compensated for in some embodiments.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: August 21, 2012
    Inventors: Ercole Rosario Di Iorio, Giulio Giuseppe Marotta, Marco Domenico Tiburzi, Pranav Kalavade
  • Patent number: 8248280
    Abstract: A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 21, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Sanyi Zhan, Daniel J. Cooley, Ligang Zhang
  • Patent number: 8249257
    Abstract: The present subject matter related to trusted computing, and more particularly, to virtual trusted platform module keys rooted in a hardware trusted platform module. Some embodiments include a trusted platform virtualization module operable to capture virtual machine trusted platform module calls and operates to generate, maintain, and utilize hardware trusted platform module keys on behalf of the one or more virtual machines. Some embodiments include virtual trusted platform module keys having a public portion on top of an private portion including an encrypted hardware trusted platform module key.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: Tasneem Brutch, Alok Kumar, Vincent Scarlata, Faraz A. Siddiqi, Ned M. Smith, Willard M. Wiseman
  • Patent number: 8250364
    Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
  • Patent number: 8249247
    Abstract: In one embodiment, the present invention includes an apparatus having a first pair of low voltage operational amplifiers to generate an output representative of an absolute value difference of first and second line voltages of a subscriber loop, and a third low voltage operational amplifier having an input coupled to the output of the first pair of low voltage operational amplifiers to filter the output and to provide a switch control signal for a switching regulator that provides a voltage used to generate the first and second line voltages. The apparatus may include additional circuits such as a limit circuit to limit the input to the third low voltage operational amplifier and one or more speedup circuits to reduce a filter time constant of the third low voltage operational amplifier during a ringing mode of the subscriber loop.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: August 21, 2012
    Assignee: Silicon Laboratories Inc.
    Inventor: Russell J. Apfel
  • Patent number: 8250334
    Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: David Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar, Shih-Lien Lu
  • Patent number: 8250456
    Abstract: A system for selecting a candidate information unit for linking to a given information unit based on the content of the given information unit. The content of the given information unit may be automatically determined and then compared to content of the candidate information unit to determine which unit of candidate information to select. When the unit of candidate information is selected, it bears a chosen given information unit and it is linked with the given information unit. The system can be used to implement a structured advertising system for the World Wide Web. Web pages (given information) are searched and indexed, producing indexed content data. This indexed content data is then ranked according to relevancy. The ranked content data are compared to content data of advertisements (candidate information) and an advertisement is selected. The advertisement is then copied onto (linked to) the Web page.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: Sanjay V. Vora, Joseph R. Kluck, William J. Nerenberg, David E. Dent, Paul M. Cohen
  • Patent number: 8245111
    Abstract: A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Zeshan A. Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Dinesh Somasekhar, Muhammad Khellah, Shih-Lien Lu
  • Patent number: 8245240
    Abstract: In one embodiment, the present invention includes a system that can optimize message passing by, at least in part, automatically determining a minimum number of fabrics and virtual channels to be activated to handle pending connection requests and data transfer requests, and preventing processing of new connection requests and data transfer requests outside of a predetermined communication pattern. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Vladimir D. Truschin, Alexander V. Supalov, Alexey V. Ryzhykh
  • Patent number: 8242993
    Abstract: A display device includes a display panel, a timing controller, a data driver and a scan driver. The display panel includes pixels respectively electrically connected to scan lines and data lines. The timing controller calculates the statistic numbers of pixels whose gray level variations between previous and current frames cross the gray-scale level of the gray point according to scan-line-signal refresh times and high-low gray-scale lookup tables, and thus selects one of the scan-line-signal refresh times and one of the lookup tables corresponding to the lowest statistic number. The scan driver outputs scan line signals to the pixels according to the selected scan-line-signal refresh time. The data driver generates pixel data according to the selected lookup table.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: August 14, 2012
    Assignee: Chimei Innolux Corporation
    Inventor: Yu-Yeh Chen
  • Patent number: 8239220
    Abstract: In one embodiment, the present invention includes a computer-implemented method to collect information to determine damage to a vehicle involved in a collision using photogrammetric techniques. When determined, this vehicle damage information, which may be in the form of crush measurement information such as a crush damage profile, can be displayed in a computer-generated view of the subject vehicle with a crush damage profile and used to estimate the impact severity. In some embodiments, based on the photogrammetric information derived, a direction of any shifting of the vehicle's components may be obtained and used along with other information to estimate a principal direction of force (PDOF) for one or more vehicles involved in the collision. Still further embodiments may be used to generate and/or audit repair estimates based at least in part on the photogrammetric information.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: August 7, 2012
    Assignee: Injury Sciences LLC
    Inventors: Scott D. Kidd, Darrin A. Smith
  • Patent number: 8239659
    Abstract: Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 7, 2012
    Assignee: Intel Corporation
    Inventors: Stephan Jourdan, Michael Fetterman, Michael Cornaby, Per Hammarlund, Ronak Signhal, Glenn Hinton
  • Patent number: 8237726
    Abstract: Message sends may be implemented in a graphics pipeline using biased graph coloring. Registers may be allocated by shaders for message sends using biased graph coloring.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: August 7, 2012
    Assignee: Intel Corporation
    Inventors: Wei-Yu Chen, Guei-Yuan Lueh
  • Patent number: 8237153
    Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: August 7, 2012
    Assignee: Intel Corporation
    Inventors: Chi On Chui, Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
  • Patent number: 8238981
    Abstract: In one embodiment, an apparatus includes a voltage regulator, an amplifier, and control logic. The regulator may receive a supply voltage and output a regulated voltage to an intermediate node. In turn, the amplifier is to be powered by the regulated voltage, while the control logic is coupled to the voltage regulator to cause a change in the regulated voltage to a safe voltage before one or more gain stages of the amplifier is to be coupled to or decoupled from an output signal path.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 7, 2012
    Assignee: Javelin Semiconductor, Inc.
    Inventor: Michael James Mills
  • Patent number: 8239667
    Abstract: Embodiments of switching between multiple operating systems (OSes) using sleep state management and sequestered re-baseable memory are generally described herein. Embodiments of the invention allow one OS to be suspended into S3 or sleep mode, saving its state to memory and turning off its devices. Then, another sleeping OS can be resumed from another location in memory by switching a memory base addressed to a sequestered memory region and restoring its device state. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: August 7, 2012
    Assignee: Intel Corporation
    Inventor: David Durham
  • Patent number: 8237869
    Abstract: A multi-standard single-chip receiver for digital demodulation of TV signals broadcasted over any of multiple digital television means, e.g., satellite, cable and terrestrial, is provided. The receiver can receive and demodulate a variety of different signal types received from one or more up-front tuners. A demodulator architecture in accordance with an embodiment of the present invention can be optimized to re-use common demodulation processing blocks for the different incoming signal types.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: August 7, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Pascal Blouin, Frederic Nicolas, David Rault, Olivier Souloumiac, Emmanuel Gautier, Stephane Faudeil, Eric Vapillon, Gaetan Guillaume, Laurent Appercel
  • Patent number: 8238233
    Abstract: In one embodiment, the present invention includes an apparatus having a first processor to execute instructions, a subordinate processor coupled to the first processor, and multiple physical devices coupled to the subordinate processor. The physical devices may each correspond to a different network communication protocol, and may each include a physical unit to forward packets to the subordinate processor while the system is in a low power mode. The subordinate processor may remain enabled during the low power mode and may include media access control functionality for handling incoming packets of different physical devices. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: August 7, 2012
    Assignee: Intel Corporation
    Inventor: John C. Weast
  • Patent number: 8227335
    Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Valery M. Dubin, Michael L. McSwiney, Peter Moon
  • Patent number: 8228431
    Abstract: In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: July 24, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Li Gao, Alan Hendrickson