Abstract: A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench.

Abstract: According to the nitride semiconductor device with the active layer made of the multiple quantum well structure of the present invention, the performance of the multiple quantum well structure can be brought out to intensify the luminous output thereof thereby contributing an expanded application of the nitride semiconductor device. In the nitride semiconductor device comprises an n-region having a plurality of nitride semiconductor films, a p-region having a plurality of nitride semiconductor films, and an active layer interposed therebetween, a multi-film layer with two kinds of the nitride semiconductor films is formed in at least one of the n-region or the p-region.

Abstract: A mask ROM small in circuit scale and low in consumption power has an n-type select transistor having a drain connected to a corresponding one of bit lines, a source connected to a data line, and a gate having a corresponding one of select signals input thereto. A p-type precharge transistor has a drain connected to a corresponding one of bit lines, a source connected to a power line, and a gate having a corresponding one of the select signals input thereto. Because the bit line is precharged by using a precharge transistor opposite in conductivity type to the select transistors, it is satisfactory to provide one precharge transistor for one bit line, greatly reducing the circuit scale.

Abstract: A method of manufacturing a semiconductor device including a die pad section, a first semiconductor chip having a surface on which a first electrode section is formed, a second semiconductor chip having a surface on which a second electrode section is formed, a support member having a surface, lead terminal sections, and a resin encapsulating body, the method including fixing a back surface of the first semiconductor chip and the surface of the support member to the die pad section; fixing a back surface of the second semiconductor chip to the surface of the first semiconductor chip and the surface of the support member; electrically connecting the first and second electrode sections respectively to the lead terminal sections; and sealing the die pad section, the first and second semiconductor chips and the support member with a resin.

Abstract: A method for testing a plurality of functional circuit blocks of a system LSI, including dividing the plurality of functional circuit blocks into at least a first test group and a second test group, wherein the first test group is tested before the second test group and wherein testing of a functional circuit block in the second test group is started immediately after testing of a functional circuit block in the first test group is finished.

Abstract: In a ferroelectric element, the ferroelectric film is prevented from deteriorating and the interconnect film from lowering in reliability. A ferroelectric element includes a first electrode, a ferroelectric film formed on the first electrode, a second electrode formed on the ferroelectric film, a first hydrogen blocking film formed directly on a surface of the second electrode, a first insulation film formed on the first hydrogen blocking film, a first opening formed in the first hydrogen blocking film exposing a part of the second electrode, a second opening formed in the first insulation film and having a greater diameter than the diameter of the first opening, and an interconnect film connected to the second electrode through the first and second openings.

Abstract: An adhesion layer for causing a plug for electrically connecting a lower wiring and an upper wiring opposite to each other with an interlayer insulating film interposed therebetween to adhere to the interlayer insulating film is formed within a through hole for forming the plug, based on a predetermined aspect ratio represented by a ratio of a depth dimension of the through hole to a diameter dimension of the through hole.

Abstract: In a duty adjustment circuit, a clock signal is frequency-divided to ½n by a frequency divider. In a first frequency doubler among n cascade-connected frequency doublers, the divided clock signal is delayed by a variable delay portion according to a control signal. The exclusive logical sum of the delayed signal and the divided clock signal in the frequency-doubling portion doubles the frequency. The average voltage of the frequency-doubled signal is detected by an average value detection portion, and is compared with a reference voltage by a comparison control portion. A control signal is fed back to the variable delay portion to cause the average voltage to become equal to the reference voltage. In this manner, a clock signal is generated from the last frequency doubler with frequency equal to that of the original clock signal, and with duty ratio adjusted to a desired value.

Abstract: The present invention provides a method for manufacturing a semiconductor elemental device wherein a first gate oxide film and a second gate oxide film thicker than the first gate oxide film are formed on a substrate provided with a device forming region comprised of silicon, comprising the steps of implanting an element for promoting a forming speed of each gate oxide film into a region for forming the second gate oxide film of the substrate; and simultaneously forming the first gate oxide film and the second gate oxide film by a thermal oxidation method, wherein in the element implanting step, the element is implanted in space of a depth equal to half the thickness of the second gate oxide film placed in predetermination of its formation from the surface of the substrate in such a manner that with the peak of a concentration distribution of the element as the center, a concentration distribution in which both sides of the peak is given twice as large as a standard deviation of the concentration distribution

Abstract: A vacuum leakage detecting device includes a process chamber for performing processes, a fluid valve, and a dry pump. The device further includes a helium gas sensor to detect helium gas in order to check vacuum leaks in potential external leak points.

Abstract: An operational amplifier including a differential input section generating a first signal as a differential voltage between two input signals; an amplifying section amplifying the first signal into second and third complementary signals; a first MOS transistor between a first supply voltage and an output node, a conduction state of the first MOS transistor controlled responsive to the second signal; a second MOS transistor between a second supply voltage and the output node, a conduction state of the second MOS transistor controlled responsive to the third signal; and a step-up section stepping up the first and second supply voltages to generate a step-up voltage higher than the first and second supply voltages, the amplifying section driven by the step-up voltage so that an absolute value of the maximum level of the second or third signal becomes larger than the absolute value of the first or second supply voltage.

Abstract: A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.

Abstract: A management system and method of a reticle in an exposing process are disclosed. A calculator calculates an accumulated dosage of an illuminating light irradiated onto a reticle used in a photolithography process. The calculator is connected to an exposing apparatus to expose photoresist on a semiconductor substrate. A comparator compares the calculated accumulated dosage with a preset reference dosage. When the calculated accumulated dosage is greater than or equal to the reference dosage, a controller suspends the photolithography process. Minimizing haze contamination on the reticle, thus preventing process failures.

Abstract: A polishing pad used for polishing the surface of a semiconductor wafer in CMP equipment, includes a support layer adhered to the top of a rotary plate of the CMP equipment, a polishing layer disposed on top of the support layer, and an adhesive layer interposed between the support layer and the polishing layer and adhesively fixing the polishing layer to the support layer. In one embodiment, the polishing support layer is a plate-shaped molded article formed of a mixture including magnetic powder and a bonding agent containing synthetic resin. In another embodiment, a protective film extends along outer peripheral side walls of the adhesive layer and the support layer.

Abstract: A wafer pattern inspecting apparatus and method are disclosed. The apparatus comprises an image sensor to acquire image data from a reference die and a sample die, an external memory to store the image data, an encoder to compress the data, a decoder to decompress the data, an internal memory device to store the compressed image data of the reference die, an arithmetic module to process the image data for the reference dies to extract a reference image data, a reference storage memory to store compressed reference image data, and a comparison module to compare the sample die image data with the reference image data to an extract defect data for the sample die.

Abstract: The present application discloses a method of cleaning a semiconductor wafer by mounting a wafer to a chuck, positioning a gas guard, defining therein a chamber having an open bottom, immediately above the layer of water, spraying de-ionized water onto the wafer while rotating the chuck at a location outside the chamber when the wafer is mounted to the chuck, to thereby form a layer of water on the wafer, and spraying a cleaning gas from a gas spraying unit disposed above said chuck through the chamber and into the layer of water to thereby cause the cleaning gas to dissolve in the layer of water, and at the same time moving the chamber across a surface of the wafer, to thereby clean the wafer, wherein said gas spraying unit includes a gas injection tube oriented to inject the cleaning gas towards the wafer mounted to the chuck, and the gas guard connected to the gas injection tube.

Abstract: A method of fabricating a ferroelectric capacitor that can inhibit ferroelectric characteristics from deteriorating includes forming a lower electrode film over from on a top surface of a plug disposed in a silicon oxide film to on the silicon oxide film; forming a paraelectric film so as to frame-likely cover a periphery of a surface of the lower electrode film with a predetermined width; forming a ferroelectric film over from on the exposed lower electrode film from an opening of the paraelectric film to on the paraelectric film in the surroundings of the exposed lower electrode film; forming an upper electrode film, in a surface of the ferroelectric film, over from on a region that faces a contact surface between the lower electrode film and the ferroelectric film to on a region that faces the paraelectric film; and etching through a mask that covers, in a surface of the upper electrode film, from a region that faces the contact surface to a region that faces the paraelectric film.

Abstract: In a method for removing a nitride layer of a semiconductor device, an etchant including about 15 to about 40 percent by volume of hydrofluoric acid, about 15 to about 60 percent by volume of phosphorous acid, and about 25 to about 45 percent by volume of deionized water is prepared. The etchant is provided onto a nitride layer that is formed on a bevel, a front side or a backside of a substrate to remove the nitride layer. The substrate is rinsed using deionized water, and then the substrate is dried. The etchant rapidly removes the nitride layer at a relatively low temperature to avoid damage to the substrate.

Abstract: To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

Abstract: The present invention discloses a portable blackbody furnace comprising a metallic body, a cylindrical cavity with a tapered end in the metallic body, a shielding plate positioned at an open end of the cylindrical cavity, at least a first heaters positioned in the shielding plate, a plurality of second heaters positioned around the metallic body, and a plurality of thermometers positioned in the metallic body. Preferably, the heat capacity of the metallic body is larger than 200 Joules/K, and has radial thickness larger than 5 mm. There are grooves formed on the outer wall of the metallic body, and the second heaters are heating wires embedded inside the grooves. In addition, the flow direction of the current between two adjacent heating wires is opposite to eliminate the magnetic field generated from the current flow.