Abstract: Some of the members constituting a semiconductor element are formed from ?-Si and an HSG forming process is implemented to form hemispherical polysilicon grains at some of the members formed from ?-Si. Thus, a semiconductor device that is achieved without requiring a great number of manufacturing steps such as film formation and etching, facilitates control of the individual steps and assures reliable electrical connection between the members and a method of manufacturing such a semiconductor device are provided.

Abstract: A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods. An address sorting circuit receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block. The word lines of the memory array are refreshed according to the second multi-bit address signal.

Abstract: In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.

Abstract: A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a vertical portion covering a side wall of the gate pattern, and a lateral portion extending from the bottom of the vertical portion over the source/drain region. Support portions interposed between the L-shaped spacers and the gate pattern support the lateral portions of the L-shaped spacers such that an air gap is defined between at least the lateral portions of the L-shaped spacers and the source/drain regions. The air gap minimizes the parasitic capacitance associated with the gate electrode of the semiconductor device.

Abstract: A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer responsive to the reference counting signal; a first buffer which stores a counted value of the dividing counter in synchronization with a second clock, when operation is by the first clock; a second buffer which stores the timing synchronizing timer value in synchronization with the second clock, when operation is by the first clock; a first adder which adds a first or second offset value to the stored value in the first buffer in synchronization with the second clock, when the first clock is suspended; and a second adder which adds a set value to the timing synchronizing timer value responsive to a carry from the first adder.

Abstract: A substrate has a collector region of a first conductivity type, and a base layer of a single crystalline structure and including impurities of a second conductivity type is located over the collector region. An emitter region is defined at least in part by impurities of the first conductivity type contained in the base layer. An emitter electrode of the first conductivity type contacts the emitter region, and at least a portion of the emitter electrode which is in contact with the emitter region has a single crystalline structure.

Abstract: A controlled release preparation of insulin and its method are provided. The controlled release preparation of insulin contains microparticles obtained by microencapsulation of uniform microcystals of insulin using biodegradable polymeric materials. Since the denaturation of insulin that may occur during microencapsulation is reduced, the stability of the preparation can be increased. Also, the ratio of insulin to a polymer carrier is increased, which is suitable for pulmonary delivery. Further, the controlled release preparation of insulin can continuously exhibit pharmaceutical efficacy in vivo in a stable manner for an extended period of time.

Abstract: An output driver may reduce coupling noise. The output driver may include a first transistor, a second transistor, and/or a noise-eliminating portion. The first transistor may have a first terminal connected to a first voltage, a second terminal connected to a first node, and a gate to which data is applied. The second transistor may have a first terminal connected to the first node and a second terminal connected to an output node. The noise-eliminating portion may be connected between the gate of the first transistor and a gate of the second transistor. The noise-eliminating portion may be a capacitor. The capacitor may substantially eliminate coupling noise introduced at the gate of the second transistor, due to coupling capacitance between the gate of the second transistor and the output node and coupling capacitance between the gate of the second transistor and the first node, by using the data applied to the gate of the first transistor.

Abstract: A hard macro cell which prevents signal delay and quality deterioration of signal waveforms without requiring excessively long wires, and a semiconductor integrated circuit using the hard macro cell. The semiconductor integrated circuit includes the hard macro cell and other hard macro cells, which are functional blocks for performing predetermined functions. The hard macro cell is provided with input/output terminals for connecting the hard macro cell with the other hard macro cells, a repeater for overcoming signal delay and for improving the quality of signal waveforms, and an input terminal and an output terminal for connecting global wires which connect the other hard macro cells to the repeater. Signals outputted from an output terminal of one of the other hard macro cells are inputted to an input terminal of another of the other hard macro cells via the global wires and the repeater.

Abstract: A chromeless photomask includes a main pattern portion and a complementary pattern portion formed in the surface of the transparent mask substrate adjacent to an outer peripheral edge of the main pattern portion. The main and complementary pattern portions are each formed by recessing a surface of a transparent mask substrate to produce respective protrusions and recesses that induce a phase difference of 180 degrees in light rays passing therethrough. The complementary pattern portion is designed to produce interference that prevents distortion in the photoresist pattern formed at a region by and corresponding to the edge of the main pattern portion of the photomask. Accordingly, the present invention provides for a relatively large secondary mask alignment margin.

Abstract: The photosensitive polymer includes a first monomer which is norbornene ester having C1 to C12 aliphatic alcohol as a substituent, and a second monomer which is maleic anhydride. A chemically amplified photoresist composition, containing the photosensitive polymer, has an improved etching resistance and adhesion to underlying layer materials, and exhibits wettability to developing solutions.

Abstract: The present optically modulated scatterer comprises a substrate, an antenna positioned on the substrate, an optical switch connected to the antenna, and an optical waveguide connected to the optical switch. The antenna includes a first conductive line and a second conductive line, the optical switch electrically connects the first conductive line and the second conductive line, and the optical waveguide can transmit an optical modulating signal to the optical switch. In addition, the antenna can be a loop-shaped antenna with two free ends, and the optical switch electrically connects the two free ends. The optically modulated scatter array of the present invention comprises a first substrate and a plurality of optically modulated scatterers positioned on the surface of the first substrate in a one-dimensional or a two-dimensional array manner.

Abstract: The present invention relates to a method and apparatus for automatically measuring the concentration of total organic carbon (TOC) in chemicals and ultra-pure water that are used in a wet etch process. The apparatus includes a sampling line extending from a processing bath, and a pump, for extracting a fluid sample from the processing bath, a buffer for filtering foreign material or air bubbles from the fluid, and an analyzer for analyzing the concentration of TOC in the fluid.

Abstract: A projected iterative descent method is used to resolve LCPs related to rigid body dynamics, such that animation of the rigid body dynamics on a display system occur in real-time.

Abstract: A mesh-shaped gate electrode is located over a surface of a substrate. The mesh-shaped gate electrode includes a plurality of first elongate wirings extending parallel to one another, and a plurality of second elongate wirings extending parallel to one another. The first elongate wirings intersect the second elongate wirings to define an array of gate intersection regions over the surface of the substrate and to further define an array of source/drain regions of the substrate. To reduce gate capacitance, at least one oxide region may be located in the substrate below the mesh-shaped gate electrode. For example, an array of oxide regions may be respectively located below the array of gate intersection regions.

Abstract: A memory system using a simultaneous bi-directional input/output (SBD I/O) circuit on an address bus line. The memory system includes a first address I/O circuit and a second address I/O circuit, which are connected by the address bus line. The first address I/O circuit may be included in a controller, transmits an address signal to the address bus line, and receives an acknowledgement signal from the address bus line. The second address I/O circuit may be included in a memory device (such as dynamic random access memory (DRAM)), transmits the acknowledgement signal to the address bus line, and receives the address signal from the address bus line. The memory system may also include an error correction circuit unit which generates the acknowledgement signal indicating if an error is present in the address signal received by the second address I/O circuit.

Abstract: A semiconductor memory device with a data output circuit that flexibly sets an initial value of a driver strength using fuses.

Abstract: A system and method of wavefront sensing with a Shack-Hartmann wavefront sensor precisely locates focal spots on a detector array, and determines the location of the lenslet array with respect to the detector array.

Abstract: In a method for testing an operation state of an electron beam inspection apparatus, an electron beam sequentially scans a plurality of scan lines in a predetermined inspection area on a substrate. A detector detects secondary electrons emitted from the scan lines and an image acquisition unit acquires inspection images corresponding to the scan lines from the secondary electrons. An image processing unit analyzes the inspection images using an initial sensitivity in order to detect defects on the scan lines. A graphic unit produces an inspection graph indicating the number of defects and an operation unit compares the inspection graph with a reference graph. A compensator compensates a sensitivity difference corresponding to a difference between the inspection graph and the reference graph.

Abstract: A method for manufacturing a liquid crystal display which reduces the number of photolithography processes is provided.