Abstract: A semiconductor device includes a die pad section, a first semiconductor chip having a surface formed with a first electrode section and a back surface fixed to the die pad section, a second semiconductor chip having a surface formed with a second electrode section and a back surface fixed to the surface of the first semiconductor chip, a support member having a surface fixed to the back surface of the second semiconductor chip and a back surface fixed to the die pad section, lead terminal sections respectively electrically connected to the first and second electrode sections, and a resin encapsulating body that seals the die pad section, the first and second semiconductor chips and the support member.

Abstract: An adhesive compound for use with a photoresist, the compound represented in accordance with the following chemical formula, A method for forming a photoresist pattern using the adhesive compound is also disclosed.

Abstract: Transition signal control for creating asynchronous timing is provided using a transition signal control circuit, which includes Muller C elements each with an inverter. The control device is constituted by a machine ring including n-stages of transition signal control circuits, a state ring including k-stages of transition signal control circuits, and a synchronous circuit for synchronizing with the machine ring by receiving a vector which is output from the state ring. When the output vector of the state ring is received, the synchronous circuit outputs a vector to the machine ring. The output vector of the machine ring and the output vector of the state ring create timings for controlling the processor, for example, asynchronously, and these timings are input to the instruction decoder, for example.

Abstract: A current mode output driver and output current control method of controlling an output current using a gate voltage are provided. The current mode output driver, which outputs data read from a memory core to a transmission line, includes a gate voltage control circuit, a bias circuit, and a driver circuit. The gate voltage control circuit generates a predetermined gate voltage in response to a current control signal. The bias circuit outputs the gate voltage as a first enable signal in an active mode, and outputs a ground voltage as a second enable signal in a standby mode. The driver circuit drives a predetermined output current in response to the first enable signal, outputs the predetermined output voltage to the transmission line according to the data, and stops its operation in response to the second enable signal. The gate voltage control circuit changes the level of the gate voltage according to a value of the current control signal and output the changed result.

Abstract: An apparatus for aligning a wafer is provided, which normally senses a flat zone of the wafer by sensors regardless of an external light so that the wafer is aligned in a set mode, in order to increase or maximize production yield. A body has all kinds of drivers. An orient chuck is provided to protrude to an upper portion of the body for rotating the wafer; a guide plate ascending and descending to slide a circumference surface of the wafer so that a center of the wafer is located on the orient chuck. A plurality of sensors sense a flat zone of the wafer being rotated on the orient chuck. A wafer carrier cassette is formed at an upper portion of the orient chuck in order to load the wafer aligned in one direction by the sensors and the orient chuck, and is supported by a plurality of frames formed at respective corners of the body.

Abstract: A method for manufacturing a semiconductor device suppresses electric charge charged up in a semiconductor layer of an SOI substrate at the time of ion implantation, preventing a BOX layer and a gate oxide from being damaged. A field oxide film is formed on a semiconductor layer formed on a BOX layer. A conductive layer is formed on the field oxide film and a gate oxide film as well. The conductive layer made of amorphous carbon is formed by sputtering and has a thickness of 5 nm to 10 nm. B+ is implanted in the interface between the semiconductor layer and the gate oxide film by an intermediate dose ion implanter. The electric charge generated in the semiconductor layer at the time of ion implantation results in FN current, which is removed through the gate oxide film and the conductive layer.

Abstract: An output buffer circuit includes first and second inverters connected to an input terminal for outputting signals having a slow rise up and fall down characteristic; a pull up control circuit that pulls up an output voltage of the first inverter and stops the pull up operation based on a level of the output signal of the first inverter; and a pull down control circuit that pulls down an output voltage of the second inverter and stops the pull down operation based on a level of the output signal of the second inverter. A first output transistor has a source connected to a first power source, a drain connected to the output terminal and a gate connected to the first inverter. A second output transistor has a source connected to a second power source, a drain connected to the output terminal and a gate connected to the second inverter.

Abstract: An integrated circuit device externally connected with a peripheral device operated by a first clock signal. The integrated circuit device includes a CPU having information on the frequency of the first clock signal, a clock generator generating a second clock signal for operating the CPU and outputting third clock signals obtained from the second clock signal and a clock halt portion receiving the third clock signals and selectively outputting only one of the third clock signals according to the information. The integrated circuit device further includes a timer activated only when receiving the one of the third clock signals and converting the frequency of the received clock signal for output and a clock synchronization serial port receiving the clock signal outputted from the timer and one of the other third clock signals, and supplying either one of the received clock signals to the peripheral device according to the information.

Abstract: A semiconductor substrate is mounted on a semiconductor alignment apparatus. A chip alignment step is performed to center a central chip on the semiconductor substrate with respect to the semiconductor alignment apparatus, and to store the coordinates thereof. A semiconductor substrate alignment is performed to virtually align the semiconductor substrate with the semiconductor alignment apparatus. At this time, coordinates of a chip adjacent to the central chip and of a number of chips in a peripheral region of the semiconductor substrate are stored in the alignment apparatus. In addition, at least two templates are located in the central chip, and images and coordinates of the templates are stored in the semiconductor alignment apparatus during the semiconductor substrate alignment.

Abstract: A diffusion furnace of semiconductor manufacturing equipment is cleaned efficiently with a cleaning gas (ClF3) by using an auxiliary cleaner. The auxiliary cleaner is inserted into an inner tube of the wafer diffusion furnace. The auxiliary cleaner has a cylindrical body that occupies a central region of the interior of the furnace but is spaced apart from an inner wall surface of the inner tube. Accordingly, the gas is confined to a peripheral region adjacent the inner wall surface. As a result, a relatively small amount of the cleaning gas is comsumed during the cleaning process.

Abstract: A contactless memory architecture has a column of bidirectional multi-bit memory cells between each adjacent pair of diffused lines in a bank. The architecture includes about half as many metal lines as diffused lines, and bank select cells at both ends of the bank. Most bank select cells connect respective metal lines to respective pairs of diffused lines. For a memory access, metal lines on one side of a selected bidirectional memory cell are biased to a first voltage, and metal lines on the other side of the selected bidirectional memory cell are biased to a second voltage. The first voltage is made higher than the second voltage to select one of the storage locations in the selected cell, and the second voltage is made higher than the first voltage to select the other of the storage locations in the selected cell.

Abstract: A test apparatus and method tests a pad conditioner of a chemical mechanical polishing apparatus. The pad conditioner test apparatus includes a main body having a conditioner mounting section that supports the pad conditioner, a conditioner head raising/lowering system that raises and lowers the head of the pad conditioner while the pad conditioner is supported on the test apparatus, and a discrimination section that detects the ability of the head to be raised/lowered in accordance with a program so that the condition of the head can be determined. The test apparatus can prevent various problems that otherwise would occur if a new pad conditioner were directly installed in the chemical mechanical polishing apparatus.

Abstract: A method for manufacturing a semiconductor device including an electrode having a lower silicon layer and an upper silicon layer which is formed on the lower silicon layer. A concentration of impurities in the upper silicon layer is higher than a concentration of impurities in the lower silicon layer.

Abstract: A silicone hyper-branched polymer surfactant is included in a rinsing solution which may be used to remove photoresist residues.

Abstract: Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operation reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing.

Abstract: A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.

Abstract: A voltage generating circuit that drives multiple output terminals in alternating positive and negative cycles has two resistor ladders, one resistor ladder generating voltages for the positive cycles, the other resistor ladder generating voltages for the negative cycles. Single-ended amplifiers are connected directly to the resistor ladders, and a switching circuit connects each output terminal to a selectable one of the amplifiers. The output terminals may be precharged to opposite potentials at the beginning of positive and negative cycles, and the resistor ladders may include switching elements that initially set all generated voltages to these potentials so that the amplifiers start each cycle with equal input and output levels, reducing overshoot and undershoot. This voltage generating circuit saves space and power in driving, for example, a display panel in a mobile telephone.

Abstract: A desired level of pressure is established in at least one chamber that forms part of a closed atmosphere, such as in a semiconductor device processing facility. A pressure control system includes at least one space increase/decrease device that has a partition which is movable to increase and/or decrease the volume of free space within the chamber(s), a pressure sensor for detecting the pressure within the chamber(s), and a controller for controlling the movement of the partition based on the detected pressure. A chamber is provided with positive or negative pressure to increase or decrease the pressure therein while the pressure in the chamber is monitored. As soon as the pressure within the chamber equals a predetermined pressure, the providing of the positive or negative pressure is stopped. The partition is moved to vary the effective volume of free space in the chamber(s) to change the pressure in the chamber from the predetermined pressure to the desired pressure.

Abstract: The semiconductor device includes a multilevel interconnection formed on a semiconductor substrate. The multilevel interconnection includes a plurality of wiring layers each of which is insulated by an insulating layer. A metal member is formed as a shielding film in a same plane as a wiring layer. As a result, the shielding layer can be formed without increasing the number of process steps.

Abstract: A semiconductor device having electrodes formed along a peripheral part thereof in a staggered arrangement of lines including inside-line, central-line and outside-line electrodes. The inside-line electrodes are octagonal or hexagonal shaped with hypotenuses on the central-line electrode and the pellet sides thereof. The central-line electrodes are octagonal or correspondingly hexagonal shaped with hypotenuses on the inside-line and outside-line electrode sides thereof. The maximum width of outside-line electrode wires between the hypotenuses of adjacent inside-line and central-line electrodes depends on the distance between centers of the inside-line and central-line electrodes, minimum lengths of the inside-line and central-line electrodes and electrode protective film, and the necessary minimum conductor interval between the central-line and inside-line electrodes.