Abstract: A ball grid array package semiconductor device having improved power line routing. The BGA package semiconductor device includes a semiconductor chip having a plurality of pads along its center, a substrate having a slot of a predetermined size along its center, and a signal line plane including a signal line pattern and a plurality of ball mounts on its one side, with the semiconductor chip being mounted on the other side. A bonding material is inserted between the semiconductor chip and the substrate to fix the semiconductor chip to the substrate. A plurality of balls are mounted on the plurality of ball mounts to be connected to an external circuit. The signal line plane is divided into two or more signal line planes including a first line plane and a second line plane. Lines for the first power are formed only on the first signal line plane, and lines for the second power are formed only on the second signal line plane.

Abstract: A photomask for use in photolithography has substrate, a main pattern at one side of the substrate, and a transparency-adjusting layer at the other side of the substrate. The transparency-adjusting layer has a characteristic that allows it to change the intensity of the illumination incident on the main pattern during the exposure process accordingly. In manufacturing the photomask, a first exposure process is carried out on a wafer using just the substrate and main pattern. The critical dimensions of elements of the pattern formed on the wafer as a result of the first exposure process are measured. Differences between these critical dimensions and a reference critical dimension are then used in designing a layout of the transparency-adjusting layer in which the characteristic of the layer is varied to compensate for such differences.

Abstract: Sealing structure for use in creating a seal between an elevator drive shaft and a loadlock chamber includes a base fastened over a hole in the bottom wall of the loadlock chamber, a fixed member fastened to an upper part of the base, a seal housing spaced above the fixed member, a cap in the form of a flexible bellows having a first end adhered to an upper surface of the fixed member and a second end adhered to a lower surface of the seal housing, one or more support shafts having upper and lower ends pivotally connected to the seal housing and the fixed member outside the cap, a seal seated in the seal housing and having an inner circumferential surface contacting the outer circumferential surface of the elevator drive shaft, and a seal cover fixed to an upper part of the seal housing. According to the present invention, uniform pressure is maintained between the shaft and the seal during assembly and operation of the apparatus.

Abstract: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur.

Abstract: In a method of optimizing a shape of an aperture, an effective light source is divided into a plurality of minute areas having same shape and size. One point light source is provided at a center of each of the divided minute areas. A normalized image light intensity slope on a wafer is obtained in consideration of a focus variation of a projection aligner for a plurality of patterns at each of the point light sources. The normalized image light intensity slope of a light intensity is used as an index. The image light intensity slope is related to an exposure amount variation of the projection aligner by one dimensional function. A common opening is selected for the shape of the aperture that is optimized for each of the patterns. The common opening is made into an optimum shape of the aperture for the patterns.

Abstract: A bandgap reference voltage circuit includes a constant-current circuit, a reference voltage output circuit generating a reference voltage according to the constant current, a power supply voltage detection circuit, and a start-up output circuit. The start-up output circuit supplies a starting potential to the constant-current circuit until the power supply voltage detection circuit detects that the power supply has reached a voltage sufficient for the constant-current circuit to maintain operation. The power supply voltage detection circuit has elements analogous to the elements in the constant-current circuit that determine this voltage, so start-up operation can occur and end reliably. The start-up output circuit includes a low-impedance path from the power supply to a node controlling supply of the starting potential, so power-supply noise does not trigger unwanted output of the starting potential after start-up operation has ended.

Abstract: A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

Abstract: An interface circuit includes a frequency divider which divides a frequency of a base clock to provide frequency-divided clock signals; a first address register which stores an address signal at a timing in which the frequency-divided clock signal is turned to high; a second address register which stores the address signal at a timing in which the clock signal is turned to low; a first data register which stores a data signal at a timing in which the clock signal is turned to high; and a second data register which stores the data signal at a timing in which the clock signal is turned to low. The data signals stored in the first and second data registers are selectively outputted.

Abstract: A memory cell array includes ferroelectric memory cells arranged in m rows and n columns, bit lines provided along a row direction, and word lines and plate line provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between the fourth row and fifth row. The arrangement allows the connecting of four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells is reduced, to suppress deterioration of the ferroelectric memory cells. The word lines may instead intersect each other between the second and third lines, so that two ferroelectric memory cells are connected to the same plate and word lines.

Abstract: Methods and specialized media adapted to the formation of a steady-state, non-equilibrium distribution of free carriers using mesoscopic classical confinement. Specialized media is silicon-based (e.g., crystalline silicon, amorphous silicon, silicon dioxide) and formed from mesoscopic sized particles embedded with a matrix of wide-bandgap material, such as silicon dioxide. An IR to visible light imaging system is implemented around the foregoing.

Abstract: In a method for forming a silicon-on-insulator FET having a contact that provides a fixed potential to a substrate, the substrate-biasing between the SOI transistor and the silicon substrate is performed via a plug. As a result, a contact hole for the substrate-biasing does not need to pass through the insulating layer, the silicon layer, and the interlayer insulating layer of the structure. Therefore, the interlayer insulating layer can be made to have shallow depth. Ions can thus be implanted to the surface of the substrate via the contact hole for substrate-biasing. The contact hole for substrate-biasing can be formed without causing an opening fault.

Abstract: A substrate processing apparatus for processing substrates prevents the substrates from contaminating as they are transferred. The apparatus includes a container, like a FOUP, for containing substrates, at least one processing chamber where the substrates are processed, a substrate transferring module including a substrate transfer chamber and at least one load port for supporting a container, and a contamination controlling system for the substrate transfer chamber. The contamination controlling system includes a purge gas supply inlet connected to the substrate transfer chamber, and a gas circulating tube for recycling the purging gas to circulate through the chamber. The substrate transfer chamber is purged using the purging gas to remove moisture and contaminating materials from the substrate transfer chamber. The formation of particles on the substrate otherwise caused by a reaction between the moisture and contaminating materials while the substrate is standing by in the container can be prevented.

Abstract: The present electromagnetic signal sensing system includes a modulating circuit for generating an electrical modulating signal, a laser electrically connected to the modulating circuit, an optically modulated scatterer coupled with the laser, a receiving antenna, a synchronous detection circuit electrically connected to the receiving antenna and a signal processing circuit electrically connected to the synchronous detection circuit. The laser generates an optical modulating signal based on the electrical modulating signal for modulating the optically modulated scatterer to generate a modulated scattering signal. The receiving antenna receives the modulated scattering signal, the synchronous detection circuit generates an in-phase signal and a quadrature-phase signal with a phase offset of 90 degrees from the electrical modulating signal, and the signal processing circuit calculates the amplitude and phase of the electromagnetic signal from the in-phase signal and the quadrature-phase signal.

Abstract: A semiconductor memory device of the invention has a first reference cell connected to a first bit line and a first word line to be controlled; a second reference cell connected to the first bit line and a second word line to be controlled; a third reference cell connected to a second bit line and the first word line to be controlled; a fourth reference cell connected to the second bit line and the second word line to be controlled; and a word line select circuit connected to the first and second word lines for selecting the reference potential to be generated in the first bit line and the second bit line by selecting the first word line or second word line. Accordingly, the influence upon a semiconductor memory device in the yields of the reference cells is reduced in a semiconductor memory device using a ferroelectric capacitor, and a more highly reliable semiconductor memory device is to be provided.

Abstract: The present invention provides a method of fabricating trench isolation structures of a semiconductor device. A conformal trench filler insulation layer is formed to fill wide and narrow trenches in a substrate. A portion of the trench filler insulation layer filling the wide trench is then removed. Next, a trench protection layer is formed on the trench filler insulation layer. The resultant structure is planarized to leave the trench protection layer over the wide width trench. Another planarization process is then carried out using the etch mask pattern and the remaining trench protection layer as a planarization stopper. Accordingly, the device isolation layer will attain a uniform planarity irrespective of the various widths of the trenches.

Abstract: A high voltage generation circuit comprises a first boosting unit, a second boosting unit, a delay circuit which delays the output of the first boosting unit as applied the second boosting unit, a pre-charge unit, and switch units which connect respective nodes in response to control signals. A voltage supply circuit is also provided that converts an externally supplied power source voltage (VCC) to a predetermined pre-charge voltage (VPP2).

Abstract: In a field effect transistor having an active region defined by a device isolation region, and a gate electrode formed over the active region, in the lateral direction of the gate electrode, the source and drain formed in the active region is narrower than the active region at least at the parts proximate to each other to create a rounding region for allowing an additional current to flow through the rounding region. This increases the on-current, with almost no increase in the off-current. The operation speed is thereby increased, without increase in the power consumption during stand-by.

Abstract: A chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a conductive wiring pattern electrically connected to the metal pad; a molding resin formed over the conductive wiring pattern; and a terminal member which is electrically connected to the conductive wiring pattern, wherein the conductive wiring pattern comprises a termial portion on which the terminal member is formed, an extended portion extending from the terminal portion and a connecting portion arranged between the terminal portion and the extended portion. The portion connecting portion between the extended portion and the terminal portion is provided with a slit, to disperse stress applied to the connecting portion.

Abstract: A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n?1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read, out from each dummy memory cell, a potential Va is developed on a bit line BL2n?1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n?1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn?1 and SAn as a reference potential.

Abstract: In a test method of a memory IC function, memory ICs of different types are prepared after a memory tester is prepared. The data related to each test method of these memory ICs is transmitted to the memory tester. Further, after a random number is generated, a test of a predetermined memory IC is executed in reply to the generated random number. It is checked whether the tests of all the memory ICs are finished or not: and the generation of the random number and the execution of the test are repeated when they are not finished, while the processing is finished when they are finished.