Patents Represented by Attorney Volentine Francos & Whitt, PLLC

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  • Method for manufacturing vias between conductive patterns utilizing etching mask patterns formed on the conductive patterns
    Patent number: 7049225
    Abstract: In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having a width which is wider than that of the structures are formed on the structures. A second insulation film is formed to cover the resultant structures without voids between the structures.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: May 23, 2006
    Assignee: Sumsung Electronics Co., Ltd.
    Inventor: Ju-Bum Lee
  • Semiconductor device having a tapered interconnection with insulating material on conductive sidewall thereof within through hole
    Patent number: 7049703
    Abstract: A semiconductor device includes a fine interconnection structure with low resistance at a through hole. A first interconnection is formed on a surface of a first layer insulating film. The first interconnection is tapered. An insulating layer is formed on the first interconnection and the first insulating film, and has a through hole that exposes an upper surface and a portion of a side surface of the first interconnection. The insulating layer covers a conductive portion of the first interconnection within the through hole. A second interconnection is provided over the insulating layer, and is electrically connected to the first interconnection through the through hole.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: May 23, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Field memory having a line memory in a memory cell array
    Patent number: 7050350
    Abstract: A field memory includes a memory cell array, a first decoder, a second decoder, a sense amplifier circuit, a transfer gate circuit, a write register and a read register. The memory cell array has a field memory for storing data and a line memory for temporarily storing data. The first decoder is coupled to the field memory for selecting a memory cell in the field memory. The second decoder is coupled to the line memory for selecting a memory cell in the line memory. The sense amplifier circuit is coupled to the, memory cell array. The transfer gate circuit is coupled to the sense amplifier circuit. The write register is coupled to the transfer gate circuit for temporarily storing data to be written in the memory cell array. The first read register is coupled to the transfer gate circuit for temporarily storing data read from the memory cell array.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: May 23, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Osamu Kuroki
  • Demodulator for demodulating digital modulated signals
    Patent number: 7046743
    Abstract: A differential detector produces, for each symbol, a phase difference between received phase information and one-symbol-delayed phase information, and delivers the phase difference to a differential circuit and a phase corrector. Another differential detector produces, for each symbol, a phase difference between the one-symbol-delayed phase information and two-symbol-delayed phase information of the received phase information. The differential circuit produces, for each symbol, phase-difference difference information from a difference between both the phase differences. A phase error detector obtains a phase error caused by a difference in the carrier frequency between a sending and a receiving digital radio apparatus, based on the phase-difference difference information and either of both phase differences. A phase corrector subtracts the phase error from the phase difference.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: May 16, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroji Akahori
  • Alignment mark structure
    Patent number: 7045909
    Abstract: A semiconductor substrate having an upper layer and an alignment mark structure formed on a surface region of the upper layer, the surface region defined by opposite first and second parallel sides extending along the upper layer, outer side walls extending upwardly from the upper layer and extending lengthwise along the side, and are defined lengthwise by alternating first and second wall portions, each of the first wall portions is spaced farther from the first side of the surface region than is each of the second wall portions, and an alignment pattern defined by openings in the alignment mark structure.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: May 16, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasuhiro Yamamoto, Takahiro Yamauchi
  • Method and memory system in which operating mode is set using address signal
    Patent number: 7042800
    Abstract: A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 9, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-gu Kang, Jong-hyun Choi, Woo-seop Jeong, Ki-ho Jang, Jung-yong Choi
  • Light emitting device
    Patent number: 7042017
    Abstract: A light emitting device includes an active layer, having a multiple quantum well structure, sandwiched between an n-type semiconductor layer and a p-type semiconductor layer. The active layer includes first and second well layers made of a nitride compound semiconductor containing In, where the second well layer emits light having a main peak wavelength which is longer than that of the first well layer, and where the growth number of the first well layer is more than the growth number of the second well layer.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 9, 2006
    Assignee: Nichia Corporation
    Inventor: Motokazu Yamada
  • Method of fabricating semiconductor device
    Patent number: 7041602
    Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating film on a semiconductor element; forming a polysilicon layer on the interlayer insulating film; implanting dopant atoms into the polysilicon layer; forming a resist layer on the polysilicon layer; forming one or more first openings in the resist layer; etching the polysilicon layer using the resist layer as a first mask, thereby forming one or more second openings in the polysilicon layer; and forming one or more contact holes in the interlayer insulating film using at least the polysilicon layer as a second mask.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: May 9, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akira Takahashi
  • Waste water treatment system
    Patent number: 7041214
    Abstract: An agent is used to treat waste water containing dimethylsulfoxide and includes a solution of a porous material at a concentration of 6500 to 7500 mg/L, where an average size of pore openings of the porous material in a range of 60–550 ?m. The agent may be used in an aeration tank of a waste water treatment system, where the aeration tank is connected to a waste water tank for collecting waste water containing dimethylsulfoxide. A sedimentation tank of the system is connected to the aeration tank via a connection pipe for biologically decomposing the dimethylsulfoxide and settling sludge produced therein, and a treated water tank of the system returns a portion of treated waste water to the waste water tank and collects the remaining treated water therein.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: May 9, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seo-Young Lee, Jong-Gyung Kim, Hyun-Suk Cho, Sung-Woo Kim, Jung-Yong Kim, Jae-Keun Seo
  • Phase-change memory and method having restore function
    Patent number: 7042760
    Abstract: A phase-change memory device includes a phase-change memory cell having a volume of material which is programmable between amorphous and crystalline states. A write current source selectively applies a first write current pulse to program the phase-change memory cell into the amorphous state and a second write current pulse to program the phase-change memory cell into the crystalline state. The phase-change memory device further includes a restore circuit which selectively applies the first current pulse to the phase-change memory cell to restore at least an amorphous state of the phase-change memory cell.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: May 9, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-nam Hwang, Ki-nam Kim, Su-jin Ahn
  • External bus controller
    Patent number: 7043592
    Abstract: An external bus controller which is configured such that, when an external device having a data width smaller than that of an external bus is connected to the external bus, the signal lines of the external bus can be freely selected. This external bus controller includes a first exchange, which converts the data width of input/output data so as to compensate for differences between the data width of the internal bus and the data width of an external device, and a second exchange, which exchanges signal lines between the first exchange and the used signal lines. The signal lines to be used are set for each external device using configuration pins or similar means.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: May 9, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makoto Nagano
  • Semiconductor contact structure and method of forming the same
    Patent number: 7041605
    Abstract: The present invention provides a semiconductor contact structure and a method of forming the same. An interlayer dielectric is patterned to form a contact hole that exposes a predetermined region of conductive material on a semiconductor substrate. A recess is formed in the conductive material exposed by the contact hole and undercuts the walls that define the sides of the contact hole such that the recess is wider than the contact hole. A contact plug fills the recess as well as the contact hole. The contact plug is maintained in position stably atop the underlying conductive material because the lower part of the contact plug is wider than the upper part of the contact plug. Accordingly, the contact plug will not fall over even if the interlayer dielectric reflows during a subsequent process.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: May 9, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-Whan Lee
  • Method of determining remaining film thickness in polishing process
    Patent number: 7039488
    Abstract: A method of determining remaining film thickness in polishing process provides a technology for controlling a polishing amount of CMP in a device isolating process with satisfactory accuracy regardless of the ratio between the area of each of device forming regions and that of each of trench regions, the type of abrasive, etc.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: May 2, 2006
    Assignee: OKI Electric Industry Co., Ltd.
    Inventor: Kazuhiko Asakawa
  • Method of manufacturing split gate type nonvolatile memory device having self-aligned spacer type control gate
    Patent number: 7037783
    Abstract: A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: May 2, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-seog Jeon, Seung-beom Yoon
  • Inspection by a transmission electron microscope of a sample
    Patent number: 7038218
    Abstract: A method of manufacturing a transmission electron microscope inspection sample. The sample is mounted into a recess in the mount and the sample is grinded to a preset target thickness. A recess for mounting the sample and a groove for separating the sample from the recess are formed on a top surface of the mount. The sample is fixed into the recess using mounting wax. The protruding portion of the sample protrudes above the mount and is grinded by the grinder. The depth of the recess is based on the target thickness of the sample. The protruding portion of the sample is grinded to the top surface of the mount.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: May 2, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-Rack Lee, Sun-Young Lee
  • Semiconductor wafer bearing alignment mark for use in aligning the wafer with exposure equipment, alignment system for producing alignment signals from the alignment mark, and method of determining the aligned state of a wafer from the alignment mark
    Patent number: 7038777
    Abstract: A semiconductor wafer has an alignment mark for use in aligning the wafer with exposure equipment during the manufacturing of a semiconductor device. The wafer is made by forming a chemical mechanical polishing target layer over an alignment mark layer, chemically-mechanically polishing the target layer to planarize the same, and prior to forming the chemical mechanical polishing target layer over the alignment mark layer, forming a dense pattern of lands or trenches in the alignment layer of dimensions and an inter-spacing preselected to inhibit a dishing phenomenon from occurring in the target layer as the result of its being chemically-mechanically polished. The lands or trenches may be disposed in at least a 2×2 array of rows and columns.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: May 2, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-chang Kim, Heung-jo Ryuk, Young-koog Han
  • Divider circuit and oscillating circuit including the same
    Patent number: 7034621
    Abstract: A divider circuit including a plurality of latch circuits which are connected in series such that each of the latch circuits is responsive to a control signal to latch data which is output from a preceding latch circuit in the series, and a logic circuit which receives the data output from the plurality of latch circuits and which outputs a logic operation result to a first latch circuit in the series of the plurality of latch circuits.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: April 25, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shuichi Matsumoto, Yoshikazu Yoshida
  • Internal step-down power supply circuit
    Patent number: 7034605
    Abstract: An internal step-down power supply circuit has an internal step-down power-supply output node, a driver, a divider circuit and a current mirror circuit. The internal node provides an internal step-down power supply potential. The driver adjusts an external power-supply potential and provides an adjusted external power-supply potential to the internal node. The divider circuit divides a voltage that appears on the internal node and provides a divided voltage. The current mirror circuit is connected to the divider circuit. The current mirror circuit compares the voltage provided by the divider circuit and a reference voltage. The current mirror circuit sets the conductance of a first transistor feeding a current in response to the reference voltage to n times of the conductance of a second transistor feeding a current in response to the voltage provided from the divider circuit, wherein n is greater than 1.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: April 25, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masayuki Otsuka, Teruhiro Harada
  • Structure of semiconductor element and its manufacturing process
    Patent number: 7034396
    Abstract: A semiconductor element includes a semiconductor substrate; a film of electrode material on the substrate at a thickness corresponding to the height of a pair of confronting electrodes standing vertical; a gap in the film of electrode material at a position so that confronting surfaces of the electrodes are formed as having a width corresponding to an interval of the confronting surfaces of the electrodes; and an insulating film in the gap. Then, a pair of confronting electrodes is formed by etching the film of electrode material. An intermediate film is formed on the pair of confronting electrodes; plugs are connected to the pair of confronting electrodes through the intermediate film; and finally wiring is connected to the plugs.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: April 25, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tsukasa Yajima
  • ONO formation method
    Patent number: 7033890
    Abstract: An ONO formation method comprises the following procedures. First, a bottom oxide layer is formed on a silicon substrate, and then a silicon-rich nitride layer is deposited on the bottom oxide layer. Then, an oxidation process is performed to react with silicon atoms in the silicon-rich nitride layer, so as to form a top oxide layer. Alternatively, the silicon-rich layer can be replaced with a combination of a nitride layer and a polysilicon layer. The oxidation process can consume the polysilicon layer into the top oxide layer, and proper oxygen is introduced into the nitride layer.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: April 25, 2006
    Assignee: Skymedi Corporation
    Inventor: Fuja Shone