Abstract: A constant current source with threshold voltage and channel length modulation comprises a set of cascade transistors and a compensation circuit electrically connected to the set of cascade transistors so as to form a feedback circuit, in which the set of cascade transistors including a first MOS transistor and a second MOS transistor, and the compensation circuit comprises a third MOS transistor, a fourth MOS transistor, a sixth MOS transistor and a seventh MOS transistor. The gate terminal of the third MOS transistor is connected to the gate terminal of the second MOS transistor. The fourth MOS transistor is connected to the third MOS transistor in serial, and the gate terminal of the fourth MOS transistor is connected to the gate terminal of the first MOS transistor, and the second terminal of the fourth MOS transistor is connected to a current-supplying circuit.

Abstract: A photoresist supply apparatus of semiconductor coating equipment fills a supply pipe with new photoresist when a used photoresist bottle is replaced. The photoresist supply apparatus includes first and second photoresist bottles, first and second gas supply pipes connected to the bottles, first and second solenoid valves disposed along the gas supply pipes, first and second purge start buttons, first and second photoresist supply pipes, first and second trap tanks to which the supply pipes are connected, a third photoresist supply pipe connected to the trap tanks, a nozzle connected to the third photoresist supply pipe, first and second level sensors disposed at an upper level of the trap tanks, third and fourth level sensors disposed at a lower level of the trap tank, first and second discharge pipes connected to the trap tanks, third and fourth solenoid valves disposed along the discharge pipes, first and second drain sensors associated with the discharge pipes, and a controller.

Abstract: A CSP type semiconductor device protects a circuit from the influences exerted by an external light on a circuit. In the CSP type semiconductor device, a light-shielding material, such as a silicone-based resin, an epoxy-based resin, or a metal, is deposited onto a side surface or a rear surface of a semiconductor chip where no circuit is formed.

Abstract: A spread-spectrum phase-locked loop clock generator includes a PLL circuit, a modulation generator, a bit stream processor and a multiplexer. The modulation generator outputs a bitstream in response to an input signal and a control signal. The bitstream processor generates bitstream signals. The multiplexer outputs one of the bitstream signals in response to a frequency deviation control signal. The PLL circuit is controlled by the output of the multiplexer.

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cells. A couple of bits of data can be stored in the memory cell, the stored data being controlled according to resistance values of first and second variable resistance regions. One of the plurality of memory cells shares its first diffusion layer with an adjacent memory cell and shares its second diffusion layer with another adjacent memory cell. The first diffusion layers of the plurality of memory cells are coupled to each other with a first conductive line extending in a first direction. The second diffusion layers of the plurality of memory cells are coupled to each other with a second conductive line extending in the first direction. The gate electrodes of the plurality of memory cells are coupled to each other with a third conductive line extending in a second direction, which is orthogonal to the first direction.

Abstract: A system is provided for adjusting a photo-exposure time of a manufacturing apparatus for semiconductor devices. The system for adjusting the photo-exposure time includes a photo-exposure unit whose photo-exposure time is adjustable according to one or more adjustment signals, a pre-exposure step influence prediction unit that obtains pre-exposure step processing information and extracts parameters that may influence a resulting pattern during photo-exposure, and provides this information as feed forward data, an inspection unit that checks processed steps during a certain period after photo-exposure and provides an inspection value as a feed back data, and a central processing unit that receives the feed forward and feedback data and, by means of a predetermined calculation method, generates the one or more adjustment signals, which are used to adjust the photo-exposure time.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference ?V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of a semiconductor substrate, and forming a plurality of test patterns in scribe regions of the substrate. The scribe regions are defined alongside the device-forming regions and separate the device-forming regions from one another. The test patterns have shapes similar to that of the main patterns. Also, one of the test patterns has a critical dimensions similar to that of the main patterns, and other test patterns have respective critical dimensions that are different from the critical dimension of the main patterns.

Abstract: A memory control circuit includes a control register having a memory capacity of m bits or smaller for setting information necessary for controlling the memory, input pins to which m-bit test data is input in parallel, an extension circuit for extending the data input to the input pins to n-bit data, and a first selection section for selectively inputting n-bit data supplied from the extension circuit or a CPU based on a mode signal to switch between a test mode and a normal mode. The memory control circuit further includes a degeneration circuit for compressing n-bit data to be output in parallel to the CPU to m-bit data, a second selection section for selecting m-bit data compressed by the degeneration circuit or lower m-bit data in n-bit data to be output to the CPU based on a switch signal, and output pins for outputting the m-bit data selected by the second selection section in parallel.

Abstract: A method of manufacturing the reticles for manufacturing a semiconductor product using a photolithographic process is relatively error free and can be carried out time in a short amount of time.

Abstract: A diode which eliminates generation of local avalanche breakdown phenomenon when static surges in the backward direction are applied and withstands electrostatic breakdown. A P-type impurity diffused region of high concentration as an anode and an N-type impurity diffused region of high concentration as a cathode that surrounds the P-type impurity diffused region, are formed on the surface of an N-type silicon well region. The surface of the N-type silicon well region on which the impurity diffused regions are formed is covered with an interlayer dielectric, and a metal interconnect layer is formed thereon, to spread to the border line of the N-type impurity diffused region and is electrically connected to the P-type impurity diffused region. Accordingly, a P-type inversion layer IP is uniformly formed in a separation area between the impurity diffused regions when static surges in the backward direction are applied, preventing local avalanche breakdown.

Abstract: There is provided a compact, high-sensitivity acceleration sensor. The acceleration sensor includes a weight 8, a pedestal 9 arranged around the periphery of the weight 8, a support frame 3 formed to have a width narrower than the width of the pedestal 9 all around its perimeter, a mass 2 attached to the weight 8 to retain the weight 8 inside the support frame 3, beams 4 connecting the support frame 3 and the mass 2 and overlapping the pedestal 9 near their ends on the side of the support frame 3, and a peripheral interlayer 12 arranged between the support frame 3 and the pedestal 9 to create a predetermined clearance between the pedestal 9 and the parts of the beams 4 that overlap the pedestal 9.

Abstract: A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.

Abstract: A method of manufacturing a semiconductor device, including forming a gate insulating film on a P type semiconductor layer, forming on the gate insulating film a gate electrode having slits at, at least an end thereof on the drain electrode forming predeterminate side, selectively implanting an N type impurity into the P type semiconductor layer with the gate electrode as a mask, effecting heat treatment to activate the impurity and integrating impurity regions in which the impurity is implanted in the slits and portions outside the gate electrode, by transverse direction thereby to form a pair of N type low-density diffused layers that overlap, at least, on the drain electrode side of the gate electrode, and forming a pair of N type high-density diffused layers spaced away from the gate electrode.

Abstract: A signal waveform detection circuit includes an amplifier circuit and a comparing circuit. The amplifier circuit has differential amplifiers connected in series. Each of the differential amplifiers has a common connection point. The comparing circuit is connected to the common connection points of the amplifier circuit. The comparing circuit includes comparing units connected to one of the differential amplifiers. Each of the comparing units has a threshold voltage generating circuit for generating signals. Each signal has a threshold voltage that is set between a maximum threshold voltage of a signal output from the corresponding differential amplifier during a maximum amplitude output and a minimum threshold voltage of a signal output from the corresponding differential amplifier during a minimum amplitude output. The comparing unit further has a comparator comparing a voltage at the common connection point with the threshold voltage.

Abstract: A semiconductor device includes a silicon layer on an insulating layer. The silicon layer has a first area and a second area. An FD-MOSFET is formed in the first area and a PD-MOSFET is formed in the second area. The semiconductor device satisfies the following formulas: the thickness of the silicon layer is 28 nm to 42 nm, the impurity concentration Df cm?3 of the first area is Df?9.29*1015*(62.46?ts) and Df?2.64*1015*(128.35?ts), and the impurity concentration Dp of the second area is Dp?9.29*1015*(62.46?ts) and Dp?2.64*1015*(129.78?ts).

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: An semiconductor integrated circuit that uses a low-frequency operation clock to implement probing for fast operation. This semiconductor integrated circuit comprises a time adjustment circuit for adjusting the pulse width of enable signals. In normal mode, the time adjustment circuit does not convert the pulse width of enable signals. However, during probing, the time adjustment circuit converts an enable signal into an enable signal with a short pulse width for testing. In normal mode, a memory control circuit operates to synchronize with an unconverted enable signal. During probing, it operates in synchronization with an enable signal converted to one with a shorter pulse width.

Abstract: A first power supply node supplies a first voltage level during a normal operational mode, and a second power supply node supplies a second voltage level during the normal operational mode. An input circuit, which is connected to the first power supply node, receives an input signal and generates a corresponding signal having the first voltage level during the normal operational mode. An output circuit, which is connected to the second power supply node, receives the signal having the first voltage level and generates a corresponding output signal having the second voltage level during the normal operational mode. A detection circuit detects an interruption in the supply of the first voltage level by the first power supply node, and electrically blocks at least one leakage current path in the output circuit during the interruption.

Abstract: A semiconductor memory device in which a local input/output line sense amplifier may be selectively enabled or disabled. The semiconductor memory device may include a memory cell array block, a redundancy circuit, a switch unit, and/or a control unit. The memory cell array block may include a local input/output line sense amplifier that operates in response to a sense amplifier enable signal. The redundancy circuit may include a redundancy local input/output line sense amplifier that operates in response to the sense amplifier enable signal. The switch unit may selectively output data output from the local input/output line sense amplifier or the redundancy local input/output line sense amplifier, in response to a first select signal and a second select signal. If the redundancy circuit operates, the control unit may generate, in response to the second select signal, a sense amplifier operation control signal that disables the local input/output line sense amplifier.