Abstract: An integrated circuit (42) provides drive signals to a piezo element (48) of a milli-actuator device (20) in a mass data storage device (10). The integrated circuit (42) includes a circuit (61) for selectively operating the integrated circuit (42) in either a voltage or a charge mode of operation. A first amplifier circuit (44) can be compensated for a variable number of piezo elements in the charge mode of operation by adjustable output impedance adjusting elements (124, 126, 138-141) that are switchably connectable into the amplifier circuit (44).

Abstract: A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set at the assembly process by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.

Abstract: A DC-DC converter circuit includes a transformer with a resonate filter or snubber connected at a primary side and a switch for controlling operation of the converter. A secondary side of the transformer includes self-driven synchronous rectifiers and an output filter. Transistors are provided at the gates leads of the rectifiers and themselves are provided with a fixed voltage at their gates so as to clamp the peak voltages across to the rectifiers.

Abstract: An amplifier (70) has a differential input stage (84,86). An output transistor (102) is connected to receive a single ended output developed by transistor 86. First (74) and second (76) current sources are connected to establish respective first and second currents in the input differential transistors (84,86) according to a predetermined ratio. First and second voltages are subtracted from the differential inputs (VM,VP) in respective differential amplifiers (88,90), and the output is derived from the output transistor having a magnitude proportional to an inverse of a product of a square of the reference resistance, a carrier mobility, and an oxide capacitance.

Abstract: A servo error detector usable in an optical disk system is provided. An envelope detecting unit (24) detects the top envelopes and bottom envelopes of RF signals SA–SH, and top envelope signals SAtop–SHtop and bottom envelope signals SAbtm–SHbtm that represent the top envelope waveforms and bottom envelope waveforms of RF signals output from an optical detector. An analog/digital conversion unit (26) converts analog top envelope signals SAtop–SHtop and bottom envelope signals SAbtm–SHbtm corresponding to all input RF signals SA–SH to digital top envelope signals QAtop–QHtop and bottom envelope signals QAbtm–QHbtm, respectively. A digital operation unit (28) performs digital operation treatment for digital top envelope signals QAtop–QHtop and bottom envelope signals QAbtm–QHbtm to generate various servo error signals.

Abstract: A retract circuit (40) for retracting a data transducer carriage assembly (17) of a mass data storage device (10) to a retracted position has a digital state machine (55) that is user programmable to operate in a selected retract mode. An analog control circuit (44) is provided for receiving control signals from the digital state machine (55) for providing analog retract signals to move the data transducer carriage assembly (70). The digital state machine (55) is user programmable to operate in constant voltage, velocity detect, float and pulse, and crash stop detect modes. Preferably, the digital state machine (55) is programmed to detect a velocity of the data transducer carriage assembly (17). The digital state machine (55) also is preferably programmed to detect an error velocity of the data transducer carriage assembly (17) from a difference of a measured voltage across the data transducer driver (22) from a predetermined voltage.

Abstract: A parameter of an integrated circuit including a first trim array and a second trim array is trimmed by measuring an initial value of the parameter, determining whether the parameter exceeds a reference value, and as long as the parameter exceeds the reference value, repetitively blowing fuses associated with binarily weighted trim elements of the first trim array to eliminate trim contributions thereof to thereby decrease the parameter by weighted amounts corresponding to a present trim array bit number value until either all fuses of the first trim array have been blown or enough have been blown to cause the parameter to be less than a ?LSB/2 weight. If the parameter then is less than the ?LSB/2 weight, a fuse of the second trim array corresponding to a present bit number is blown to increase the parameter to greater than a +LSB/2 weight. The procedure is repeated until all fuses in one trim array have been blown, to thereby minimize the number of residual trim elements.

Abstract: An integrated circuit functionality test determining shorts between adjacent pins of all the IC pins while simultaneously determining pin continuity in only three steps. The process includes categorizing all pins of the IC into three sets of pins. One set of pins is connected to digital instruments, a second set of pins is connected to 0 volts, and a third set of pins is left open. The digital instruments sink current in parallel from the first set of pins to identify any shorts of the first set of pins. The process is repeated for each of the other two sets of pins. For IC packages having double and quad terminal positions, each terminal position is treated like a single terminal position, and the measurements of the respective sets of pins of each terminal position is measured in parallel.

Abstract: The present invention comprises a pair of circuits (171, 172) within the first stage (100) of an AC signal pre-amplifier. The present invention reduces the current mismatch at the base of the first stage transistors (141, 142, 143, 144) resulting in faster switching times by reducing input stage offset and, hence improving input dynamic range.

Abstract: Devices being controlled electronically via physical manipulation often display a resonance. In many circumstances, the frequency range of operation is not close to the resonance frequency. In these cases, the resonance can be removed through the use of simple compensation techniques such as filters. However, when the resonance frequency is close to the frequency range of operation and when the resonance frequency can change depending on temperature, time, and physical position of the device, simple compensation techniques cannot be used. The present invention presents a non-mechanical technique for providing compensation for devices with a shifting resonance. The non-mechanical technique allows for the compensation to be performed via computation.

Abstract: A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary technique utilizes a composite filter for a faster settling, lower noise resolution filter in a parallel configuration with a slower settling, higher noise resolution filter. As a result, valid data can be received faster for processing by the analog-to-digital converter. In addition, a composite digital filter circuit can include a three filter configuration including a fast-settling, low resolution first filter, a slower-settling, higher resolution second filter, and an even slower-settling, even higher resolution third filter, each of the filters configured in a parallel arrangement. Additional or fewer filters can also be provided. Moreover, the gain of each filter path can be suitably matched to the gain of any other filter path in the digital filter circuit to provide a filter output having an equalized gain regardless of the filter path selected.

Abstract: In one embodiment, an integrated differential isolation loss detector is disclosed that generates a first temperature that is a function of a high side current and a second temperature that is a function of a low side current. A temperature sensor senses the difference between the first and second temperatures and provides an output signal that is indicative of the magnitude and the polarity of the sensed difference. A controller receives the output signal and if the difference is greater than a predetermined magnitude the high side current, the low side current, or both can be disconnected from the load. In another embodiment, an integrated differential isolation loss detector is disclosed that includes a first temperature difference generator that generates first and second temperatures where the difference between the first and second temperatures is a function of the magnitude of the high side current.

Abstract: The present invention provides improved line and load regulation of a switching-mode power converter (300) without requiring additional capacitors (255), either internally or externally, to stabilize the control loop. The present invention can provide this by integrating a digital compensator (375) with the pulse-width modulator (“PWM”) of the switching-mode power converter. Such a compensator (375) can include comparators (310 and 330), digital circuits (340), and resistors (215, 220, 320, and 325).

Abstract: An output stage circuit is configured for enabling an output of an amplifier circuit to be pulled upwards and/or downwards to or beyond an upper power supply or below a lower power supply. The exemplary output stage circuit comprises a pair of output transistors configured to provide an output voltage, and a controlled resistive circuit. The controlled resistive element is configured to enhance the gain of the output stage circuit by modifying the dynamic impedance effect of the upper output transistor during pull-up operation, or the lower output transistor during pull-down operation. During normal operation, the controlled resistive element operates with low resistance, e.g., acts as a “short,” but during the pull-up or pull-down operation the controlled resistive element can be configured to add resistance to modify the dynamic impedance of the upper or lower output transistor.

Abstract: An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.

Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.

Abstract: A video correction system and method are disclosed that provide video correction for an input signal. The system includes a logarithmic converter that creates a logarithmic representation of the input signal. A configurable corrector/converter comprises a plurality of associated components operative to process the logarithmic representation of the input signal. The configurable corrector/converter produces an output signal having at least one desirable signal characteristic. A switch control selects a configuration for the corrector/converter. The configuration indicates at least one of the plurality of associated components that will process the logarithmic representation.

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: The present invention includes a plurality of FETs (211, 212, 213, 214, 215, 216, 217) including an operational amplifier with additional FETs (218, 219, 220,221) arranged as current mirrors, and a sense FET (101), and a current sensed at FET (101) is amplified, compared to a reference signal, the difference current derived from the amplified sense current and reference signal being amplified and provided at an output for use in control applications.