Abstract: A technique to implement removal of dead time control circuitry from the back-end of a digital switching amplifier system 100 and add dead time control circuitry on the front-end digital modulator chip. The front-end dead time control circuitry adaptively adjusts timing of the output PWM control signals 124 to optimize performance and power consumption, i.e. operate with minimum dead time for all transitions. The front-end dead time control circuitry controls all propagation delays associated with the digital switching amplifier system 100.

Abstract: A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a delay line (21). A first control signal (DOWN) is produced a in response to represent a first time at which the first pulse has progressed entirely through the delay line (21) and a later second time at which a next second pulse of the reference clock signal (CKref) arrives at a first input of the phase detector (24A). The delay of the delay line (21) is reduced in response to the first control signal (DOWN). A second control signal (UP) is produced in response to the status to represent a third time at which the second pulse of the reference clock signal (CKref) arrives at the first input of the phase detector (24A) and a later fourth time at which the first pulse of the reference clock signal (CKref) has progressed to the end of the delay line (21) and is used to increase the delay of the delay line (21).

Abstract: The present invention covers circuits to achieve high data rate writing.

Abstract: Parametric testing of an integrated circuit chip includes pressing first, second, and third contact elements (PRB-1,2,3) against first, second and third terminals (P1–3), respectively, of the integrated circuit and forcing first, second, and third reference currents (Iref) through first, second, and third circuit paths each including a corresponding ESD diode. Each path includes two of the contact elements, two associated contact resistances, and one of the ESD diodes. First, second, and third voltages (Vm1–3) are measured across the three circuit paths. Three equations representative of the three voltages are simultaneously solved to determine three contact resistances between the various contact elements and integrated circuit terminals. The voltages across the three contact resistances are computed by multiplying them by parametric test currents and are added to or subtracted from measured voltages of the contact elements to obtain accurate values of voltages of the integrated circuit terminals.

Abstract: A buck regulator switching power supply (10) selectively enabling a low side device to effectively recharge a bootstrap capacitor (Cboot) during a high duty cycle of operation. The switching power supply (10) includes a gate driver (12) driving a gate of a high side FET (Q1) responsive to a controller circuit (14). Controller circuit (14) includes a controller (16) responsively controlled by a comparator (18). Comparator (18) senses the charge of the charging side of the bootstrap capacitor (Cboot) as compared to a voltage (Vref). The comparator (18) also responsively generates an output signal on an output line (20) as a function of the voltage at the phased output.

Abstract: A feedback circuit has an optical coupler with a feedback gain control. The feedback gain control includes an active element connected to vary current flow depending on changes in gain of the optical coupler.

Abstract: A fly height controller (10FHC; 10FHC?) for controlling the fly height of a read/write head assembly (15) in a disk drive (20) is disclosed. A heat element resistor (30) is disposed within the read/write head assembly (15). The fly height controller (10FHC; 10FHC?) includes registers (32R, 32W) for storing digital data words corresponding to the desired drive levels to be applied to the heat element resistor (30) during read and write operations. The registers (32R, 32W) are selectively coupled to a steady-state digital-to-analog converter (DAC) (36), depending upon whether a read or write operation is occurring; the output of the steady-state DAC (36) is applied to a voltage driver (40), which in turn drives current into the heat element resistor (30). Overdrive and underdrive transistors (44P, 44N) are provided to overdrive and underdrive the input to the voltage driver (40) in transitions between read and write operations.

Abstract: An information storage and retrieval system (40) and method for operating same has a host device (42) and an information storage device (41), which includes mass data storage means (54), such as a DVD, a DVD RAM, CD-ROM, alone, or in combination. The information storage device (41) includes a cache memory (48) for holding data as it is being written to the mass data storage means (54). The host device (42) is connected to the cache memory (48) to control a size of the cache memory that can be utilized to hold the data to be written to the mass data storage means (54), to control, for instance, the flush, seek, busy, and/or overhead times of the information storage device (41).

Abstract: A bandwidth limited sampling circuit of high linearity may be implemented by using a first circuit portion to limit the bandwidth of the input signals, and using a second circuit portion to sample the bandwidth limited input signal. The first circuit portion and the second circuit portion may be implemented using separate components. In an alternative embodiment, bandwidth limiting is implemented by taking a difference of a sampled input signal from a sampled high frequency components of the input signal.

Abstract: An apparatus for compensating operating current in an amplifier device when supply voltage to the amplifier device decreases below a predetermined value at an input voltage supply locus includes: (a) A first control circuit coupled with the input voltage supply locus. The first control circuit generates an output signal at an output locus when the supply voltage decreases below the predetermined value. (b) A second control circuit coupled with the output locus and coupled with the amplifier device. The second control circuit effects the compensating in response to the output signal.

Abstract: A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which includes a sample-and-hold circuit (22), an analog-to-digital converter (23), and the functions of a digital-to-analog converter (DAC) (25), an adder (24), and a gain stage (27) at which a residue signal (RES) is generated for application to the next stage (20) in the sequence. A multiplying DAC (28) performs the functions of the DAC (25), adder (24), and gain stage (27) in the stage (20), and is based on an operational amplifier (29). Sample capacitors (C10, C20) and reference capacitors (C122, C222) receive the analog input from the sample-and-hold circuit (22) in a sample phase; parallel capacitors (C121, C221) are provided to maintain constant circuit gain.

Abstract: An improved method of monitoring the output power provided by a switch mode power converter that reduces the overall cost of the converter. The method includes initiating a soft-start procedure for a first output voltage in the event the first voltage channel is enabled. When the first voltage level comes within regulation, a delay counter counts a predetermined number of clock cycles. In the event a second output voltage channel is enabled between the time the first channel is enabled and the time the first voltage comes within regulation, a soft-start procedure is initiated for the second voltage and the delay counter re-starts when the second voltage comes within regulation. After the delay counter finishes counting, the first and second voltages are considered stable and a single Power-Good signal is asserted.

Abstract: A voltage feedback (“VF”) operational amplifier (“op-amp”) that includes a circuit operable to dynamically bias pre-driver transistors at the op amp output stage. This arrangement provides a dynamic bias from a common base gain stage (302) to the pre-drivers (338, 339) of the output stage (303) so that higher slew rate is achieved with minimal discontinuity in the signal.

Abstract: Systems and methods for determining coefficients a filter are disclosed. The filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distnbuted values for the sine and cosine functions in the range of 0 to ?. The inverse of the input value is computed using an inverse memory lockup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal. Thus, the coefficient is computable in real-time without the use of previously computed and stored coefficients.

Abstract: A write driver 100, 200, 300 is implemented to provide near-ground common mode output voltages to produce a more symmetrical head voltage swing (i.e. ±0.4V from ground to ±5V supply voltages). These features help to reduce the effects of common mode impedance associated with the interconnection to the disk drive head to improve overall performance. Lower jitter at high data rates can be achieved when compared to prior art techniques for implementing current mode write drivers. Further, the matched impedance between the write driver 100 and the interconnection 106 eliminates unwanted reflections. ECL level voltage swings (200–500 mV) have replaced more conventional CMOS level voltage swings (5V) to further reduce overall power dissipation associated with the write driver. The small ECL level switching further maintains constant power dissipation with changes in operating frequency and results in less NTLS effects due to quieter supplies.

Abstract: A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of integrated circuit chip area, without requiring analog calibration circuits. The DAC calibration system includes a main DAC to be calibrated, a memory, and calibration logic circuitry for performing arithmetical operations. The memory stores a predetermined number of digital code values in respective memory locations, which are indexed by corresponding voltage values. The digital code values represent DAC input code values which, when applied to the main DAC, would generate the corresponding index voltage values as DAC output voltage levels. The stored DAC input code values and the corresponding DAC output voltage levels, which are determined using an external tester, define piecewise linear (PWL) breakpoint code values of a PWL approximation of the DAC transfer function.

Abstract: A class-D amplifier circuit (30; 30?) providing improved open-loop error for base-band frequencies, such as the audio band, is disclosed. The amplifier circuit (30; 30?) includes a comparator (35) for generating a pulse-width-modulated output signal that is applied to an output power stage (37). An LC filter (32) is at the output of the power stage (37). The amplifier circuit (30; 30?) includes a loop filter having multiple feedback loop paths, with at least one feedback loop path coupled to the output of the power stage (37), and optionally, at least one feedback loop path coupled to the output of the LC filter (32). The transfer function (Hmae(s)) of the loop filter has a real part that has a much steeper slope (on the order of 80 dB/decade) at frequencies above the pulse-width-modulation switching frequency than the slope of its magnitude characteristic at frequencies below this switching frequency.

Abstract: The present invention discloses a circuit used to couple an input signal to an amplifier circuit. The circuit may contain a diode bridge coupled to an adjustable bias circuit. The current through the bias circuit can be adjusted such that the resistance of the diode bridge can be dynamically configured to change the sensitivity of the diode bridge. The bias circuit may be configured to produce a variable amount of current based on a voltage signal. In another aspect of the present invention, the output from the diode bridge is coupled to an amplifier via a clamp circuit designed to prevent the amplifier from overloading.

Abstract: A system and method of motor control enable improved motor control by controlling a phase winding to float or enter a high impedance state prior to activating phase detection of the phase winding. Because the phase winding floats prior to phase detection, the effect residual current coupling in such phase can be mitigated and thereby help improve motor operation.

Abstract: Disclosed are methods and circuits for providing a bandgap reference in an electronic circuit having a supply voltage and ground. The methods include steps for generating a bandgap reference current, mirroring the bandgap reference current, summing the mirrored currents, and modulating and outputting a bandgap reference voltage from the sum. Representative preferred embodiments are disclosed in which the methods of the invention are used in providing under-voltage protection and in providing a regulated output voltage. Circuits are disclosed for a bandgap reference voltage generator useful for providing a bandgap reference voltage in a circuit. A first current mirror for provides current from a supply voltage. A bandgap reference current circuit between the first current mirror and ground is configured for deriving a bandgap current proportional to absolute temperature. A second current mirror and control circuit are provided for summing the mirrored currents and modulating a bandgap reference voltage output.