Abstract: An external interface for a microprocessor system uses a programmed configuration bit to establish the functionality of a computer port, which improves external interface data transfer speed and input/output power consumption. In particular, the configuration bit allows the microprocessor user to establish the computer port as a memory port, input/output port or the like. The configuration bit is provided to the computer port at system power up or reset. Moreover, the configuration bit may be stored in flash memory and provided to the microprocessor computer port or, in the alternative, the configuration bit may be provided to the computer port directly via the microprocessor bus interface.

Abstract: A baud clock (15) for use by a serial communication interface (67) is generated by dividing a base clock of the serial communication interface by one of a plurality of possible composite divisors (DEG). Each composite divisor is indicative of a minimum time interval by which adjacent pulses of the baud clock are to be separated, and further indicates that at least one pair of adjacent pulses within each symbol interval of the baud clock are to be separated by an extended time interval which is longer than the minimum time interval.

Abstract: The present invention comprises a combination of a new circuit topology utilizing microcontroller (202, 302) and a modified logic control circuit which enables the replacement of a Schottky diode, commonly used in series with AC adapter, by a MOS transistor switch (212, 312) to implement airline mode operation of a system, with the added benefits of more efficient power dissipation and minimization of sparking or arcing at the power input terminal.

Abstract: Disclosed is a circuit and method for generating a tail current for a main reader amplifier (200) input stage using a scaled master differential stage (160) with a given offset to force a given output current, preceded by a balanced stage (150) to get a balanced offset. Current must be set by a feedback arrangement in the dummy master stage (160) which is a scaled version of the main reader amplifier input stage (200). The current derived in the dummy master stage (160), when appropriately scaled and used as the tail current of the main reader amplifier (200) input stage provides a precisely controlled gain.

Abstract: A voltage regulator includes a two-stage feedback circuit for driving a controller formed by a transistor 10. The feedback circuit includes an error amplifier 30 and an output amplifier 20, a simple compensating circuit in the form of a resistor RSZ inserted between the inverting input 22 and the non-inverting input 24 of the output amplifier 20 resulting in a high phase reserve of the feedback circuit. The resistor RSZ limits the gain of the error amplifier 30 for small load currents by reducing its effective output impedance. This compensating circuit results in the two-stage feedback circuit being highly stable even when very low load currents are involved. This now makes it possible to achieve a very simple linear voltage regulator architecture totally integrated on a single chip. It is especially in battery-powered handhelds such as e.g.

Abstract: A two-phase non-overlapping clock generator (12) generating a sampling signal (20) utilizing a three transistor NAND gate (50). The NAND gate of the present invention eliminates one large PMOSFET (46), and has one NMOSFET (52) driven by the other phase and having its source grounded. The present invention yields substantial improvement on the jitter of the clock phases. Both rising and falling transitions are improved because of the greatly reduced self-loading of the NAND gate. Overshooting is eliminated, and the NAND gate body effect is minimized, providing enhanced jitter performance of the sampling signal and improving a signal to noise ratio (SNR). The principle of the present invention are also embodied in a NOR gate (70).

Abstract: An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.

Abstract: An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.

Abstract: An apparatus for improving protection of a battery pack when the battery pack is in a very low power state, the battery pack including a plurality of battery cells coupled to present an output voltage at a battery potential locus and a protection device for providing a plurality of safeguards to protect the battery pack, affects operation of the protection device to control at least one safeguard and includes a current sensing unit coupled with the plurality of battery cells and with the protection device. The current sensing unit senses a battery traversing current associated with at least one battery cell. The current sensing unit generates an alerting signal when the battery traversing current exceeds a predetermined value. The protection device enables the at least one safeguard in response to the alerting signal.

Abstract: Multiple battery systems and switching networks are provided for portable electronic devices. A single switching cell is provided per battery and a load switch coupled to a battery power bus to achieve proper connectivity and isolation between batteries, a load and a charger. The single switching cells are configured as a back-to-back MOSFET switch devices. The charger is also coupled to the battery power bus and can be enabled when AC power to the portable electronic device is not available. The present invention facilitates selective connection of battery packs in a multiple battery system to a load or a charger, while still maintaining isolation between battery packs, the load and the charger.

Abstract: A low-order polyphase interpolation filter, such as for decoding video and image signals, employs interpolation to facilitate sample rate conversion from a first rate to a second rate, which can be greater or less than the sample rate of the input signal. The interpolation applies interpolation coefficients, which are non-linear with respect to an associated positioning vector, to a set of input samples to provide desired scaling and/or conversion of the input sample into the desired output sample.

Abstract: An amplifier (10?) has a first amplifier stage (14) for producing a control current (IX) in response to an input voltage. A second amplifier stage (16) has first (46) and second (38) transistors. The first transistor (46) is coupled to receive the control current (IX) and is operable to produce a control voltage. The second transistor (38) is coupled to receive the control voltage and operable to produce an output current. A nonlinear resistive element (50) is coupled to the first transistor (46) to add a nonlinear function of the control current (IX) to the control voltage. The nonlinear resistive element (50) may include a third transistor connected between the first transistor (46) and a reference potential, operable to receive the control current (IX) and to generate the nonlinear function thereof.

Abstract: An improved EEPROM device and method for providing a lower device programming voltage is disclosed. An exemplary EEPROM device is configured with a modified drawing layer comprising one or more serrated elements configured underneath a tunneling region of the EEPROM device. The serrated elements can comprise regions having at least one acute angle structure within the active mask drawing layer configured to provide a restriction of the oxygen used to grow the gate oxide that determines the programming voltage of the EEPROM device. In addition the serrated elements can also be configured with at least two acute angle thin oxide regions configured in a staggered arrangement to allow for misalignment between the active layer and the polysilicon layer such that at least one acute angle thin oxide region is found in the tunneling region underneath the polysilicon layer of the tunneling region. As a result of a thinner gate oxide region being formed, a lower programming voltage is needed by the EEPROM device.

Abstract: The tristateless bus interface communication scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a low power embedded system bus architecture is provided with a bus interface connected to one or more peripheral interface using logic processes to enable microcontroller-based products and other components and devices to achieve a low power data transmission between central processors and peripheral devices. In accordance with an exemplary embodiment, a low power embedded system bus architecture comprises logic devices, for example, an OR gate for passing through only data from a selected peripheral device. To facilitate the throughput of data, the non-selected peripheral devices may only provide logic zero to the OR gate. The logic device arrangement may comprise any combination of logic devices which performs the function of eliminating the need for tristate buffers.

Abstract: Disclosed are methods and apparatus for over-current detection in PWM power stages. Disclosed methods and apparatus provide over-current detection with adaptive filtering according to the pulse width of the PWM input signal. Methods and apparatus for their implementation are described for detecting the pulse width of a PWM signal in the PWM circuit. According to the detected pulse width, a digital delay less than the pulse width of the PWM signal is selected from among a plurality of available digital delays. Further, an over-current condition in the PWM power stage is detected. The detected over-current signal is filtered by means of the selected digital delay and an over-current detection result is output.

Abstract: The present invention discloses an impedance matched low noise amplifier circuit (10) comprising a serially coupled first resistor (R1) and first transistor (R0), a serially coupled second resistor (R2) and second transistor (R1), a resistive sensor (RMR) coupled to the first transistor (R0) and the second transistor (R1), wherein the first resistor (R1) and the second resistor (R2) are coupled, and a transconductance feedback block (GM) coupled to the resistive sensor (RMR) and to the serially coupled resistors (R1, R2) and transistors (R0, R1).

Abstract: In a method of communicating data via a bus between several modules connected to the bus in accordance with the source synchronous clock principle the data is applied from the modules to a data bus as controlled by the system clock signal A source clock signal generated by each of the modules is communicated spaced in time from the data on a source clock line. The time spacing between the data applied by a module to the data bus and the source clock signal generated by this module and applied to the source clock line can be varied as a function of characteristic parameters of the modules connected to the bus with the aid of an adjustable delay member.

Abstract: Disclosed is a circuit and method for reducing output swing in a sigma delta modulator. The quantizer output swing reduction circuit and method of the present invention advantageously enables the modulator to have a larger input/output swing range without degrading the SNR and SFDR performance. One embodiment of the present invention comprises a conventional sigma-delta modulation circuit (100) and a quantizer swing reduction block (210). The quantizer swing reduction block (210) comprises an input signal Vx (216), a signal processing block (214) with transfer function H3 and another signal processing block (215) with transfer function H2*H3.

Abstract: Voltage regulator with an output transistor MP1, including a first PMOS FET, whereby the input voltage Vdd of the voltage regulator is applied to the source of the output transistor MP1 and where the drain of the output transistor MP1 constitutes the output of the voltage regulator. The voltage regulator, furthermore, includes a regulation circuit 1 that may, for example, consist of an error amplifier and that controls the output transistor in such a way that the least possible deviations between the output voltage Vout and the target output voltage are allowed to occur.

Abstract: A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed implementation of the phase-locked loop (25) includes a voltage-controlled oscillator (30) having an even number of differential stages (31) to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit (27) includes two adder legs that generate select signals applied to first and second multiplexers (40a, 40b), for selecting among the clock phases from the voltage-controlled oscillator (30). The outputs of the first and second multiplexers (40a, 40b) are applied to a two-to-one multiplexer (46) which is controlled by the output clock signal (CLK1), to drive clock edges to a T flip-flop (48) to produce the output clock signals (CLK1, CLK2).