Abstract: One aspect of the present invention provides a motor control system that includes a linear control system operative, in a linear mode, to provide a plurality of control signals for driving an associated motor based on an error signal. The system also includes control logic operative, in a pulse-width modulation (PWM) mode, to provide the plurality of control signals for driving the motor, at least some of the plurality of control signals being pulse-width-modulated signals based on the error signal. An error system generates the error signal based on an indication of a sensed electrical characteristic of the motor relative to a predetermined reference signal. A feedback network is coupled across the error system. The feedback configured to have transfer function characteristics that substantially match responses in the linear mode and the PWM mode of motor control system, which facilitates transitions between the linear mode and the PWM mode.

Abstract: An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises a shift register (SRRD; SRWT) for storing a sequence of bits. The sequence in the shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a clock cycle to the shift register for selected data operations with respect to any of the word storage locations. The selected data operations are a data read or a data write. In response to each clock cycle, received from the circuitry for providing the clock cycle, the shift register shifts the sequence. Further, one bit in the sequence corresponds to an indication of one of the memory word storage locations from which a word will be read or into which a word will be written.

Abstract: Oscillator circuit with an LC resonant circuit 1, an activating component 2 connected to the LC resonant circuit 1, which serves to compensate for the losses occurring in the LC resonant circuit 1, where the series-configuration of both the LC resonant circuit 1 and the activating component 2 is connected by way of a current-defining element, which sets the current flowing between a first voltage VDD and a second voltage VSS, which is different from the first voltage VDD.

Abstract: Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array coupled between the comparator inputs and multiple input voltage sources, a plurality of first switching elements, and control logic/drive circuitry coupled between the comparator output and the first switching elements. The first switching elements connect a selected input voltage source to a load. The comparator compares the voltage levels of the respective voltage sources, and provides a voltage indicating which one of the voltage sources is operational to the control logic/drive circuitry, which applies control signals to the first switching elements to connect the operational voltage source to the load. The symmetric resistor array and a plurality of second switching elements assure that symmetric trip voltages with hysteresis are provided to the comparator.

Abstract: The present invention discloses a level shifter circuit (20) comprising a serially coupled first device (M3) and second device (M5), a serially coupled third device (M4) and fourth device (M6), a parallel coupled first pull-up device (M9) and second pull-up device (M10), a plurality of nodes (N1–N4), and a set-reset latch (22) comprising a first gate (I1) and a second gate (I2), wherein the first device (M3) is coupled to the first pull-up device (M9) via a first one (N1) of the plurality of nodes, wherein the second device (M5) is coupled to the first gate (I1) via a third one (N3) of the plurality of nodes, wherein the third device (M4) is coupled to the second pull-up device (M10) via a second one (N2) of the plurality of nodes, and wherein the fourth device (M6) is coupled to the second gate (I2) via a fourth one (N4) of the plurality of nodes.

Abstract: A fixture for supporting a plurality of semiconductor chips during the thermal cycling of the chips, including a fluid-permeable bottom screen, a chip-cavity-defining plate supported against a top surface of the bottom screen, a lower attaching mechanism for attaching the chip-cavity-defining plate to the top surface of the bottom screen, and a removable fluid-permeable top screen attached to a top surface of the chip-cavity-defining plate to cover the plurality of holes and chips therein.

Abstract: A dual-mode positioning driver for a voice coil motor in a disk drive system is disclosed. Linear prestage drivers and pulse-width-modulated prestage drivers are both coupled to power transistors arranged in an “H” bridge for driving the voice coil motor. The positioning driver is thus operable to drive the power transistors in either a linear mode or a pulse-width-modulated class D mode. In a transition period while switching from the pulse-width-modulated mode to linear mode, comparators compare the phase voltages in the “H” bridge with a reference voltage. The outputs of the comparators are applied to the PWM output amplifiers to drive the power transistors, so that the phase voltages are preconditioned toward their linear bias points. Discontinuities in the drive current through the voice coil motor are minimized as a result.

Abstract: Disclosed are methods and circuits for providing a bandgap reference in an electronic circuit having a supply voltage and ground. The methods include steps for generating a bandgap reference current, mirroring the bandgap reference current, summing the mirrored currents, and modulating and outputting a bandgap reference voltage from the sum. Representative preferred embodiments are disclosed in which the methods of the invention are used in providing under-voltage protection and in providing a regulated output voltage. Circuits are disclosed for a bandgap reference voltage generator useful for providing a bandgap reference voltage in a circuit. A first current mirror for provides current from a supply voltage. A bandgap reference current circuit between the first current mirror and ground is configured for deriving a bandgap current proportional to absolute temperature. A second current mirror and control circuit are provided for summing the mirrored currents and modulating a bandgap reference voltage output.

Abstract: In the synthesis of frequency channel spacing in an RF transmission signal, a raster component of the desired frequency channel spacing is provided by an integer IF frequency synthesizer (44). Because the frequencies associated with the IF synthesizer are lower then those associated with an RF frequency synthesizer (48), the IF synthesizer can incorporate the desired raster using a lower feedback divisor (N) than can the RF synthesizer.

Abstract: The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.

Abstract: An apparatus for handling high speed data communication signals in at least one input channel. Each communication signal is encoded in signal excursions in at least one predetermined format. The apparatus includes: (a) at least one input locus coupled with each input channel for receiving the signals; (b) at least one output locus for presenting selected communication signals in a desired format in at least one output channel; and (c) a plurality of treating circuits for treating the signal excursions in a plurality of formats that include the predetermined format and the desired format. Each treating circuit is coupled with at least one respective input locus and at least one respective output locus. The apparatus presents sufficiently low capacitance between input loci and output loci to impart substantially zero time delay to the communication signals.

Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.

Abstract: A DC—DC converter can supply a stable output voltage from an input voltage with the power supply voltage varying along with the supply of the power and can maintain a high voltage conversion efficiency. The DC—DC converter includes an inductive element and the first-fourth switches connected to both terminals of the inductive element, the first and second switches are turned on and off periodically corresponding to the input voltage. When the input voltage goes below a prescribed reference level, a first control signal that keeps the first switch constantly on is generated by a feedforward control circuit to turn on the third and fourth switches periodically corresponding to the output voltage so that the output time of the third switch is generated by a feedback control circuit to switch the voltage increasing operation and the voltage increasing/decreasing operation corresponding to the input voltage.

Abstract: A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are precisely matched to those of the dummy delay line (40). Tap points of the dummy delay line are connected to inputs of the watchdog circuit (32), which operates to generate control signals (34A,B) applied to control the phase detector (25 and the charge pump circuit (30). Tap point signals of the delay line (20) are decoded to produce clock signals (52) for a pipeline ADC (54).

Abstract: The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.

Abstract: A resistor (or a component with impedance that does not change) is provided across the output of an amplifier, which minimizes the changes in the amplification factor of an amplification circuit during operation.

Abstract: The present application describes a frequency compensation scheme for a linear voltage regulator circuit, or its special case, a low-drop out voltage regulator (LDO). According to one embodiment, the frequency compensation scheme includes two circuits, an inner loop compensation circuit (240), and a circuit (245) at the output in parallel with one of the resistors of the output voltage divider (235). These two compensation elements (240, 245) are not interdependent and may be adjusted separately to provide more optimal frequency compensation. Advantages include smaller compensation circuit elements, die or board area savings, better phase margin over process technology variations and operating conditions, and ease of design adjustment.

Abstract: A system and method provide overshoot protection to facilitate driving a load by output circuitry in response to a transition from a first operating mode to a second operating mode. The overshoot protection occurs by masking an input bias from biasing the output circuitry for an initial part of the second operating mode based on a transition to the second operating mode, and then allowing the input bias to bias the output circuitry in a desired manner in a subsequent part of the second operating mode.

Abstract: A segmented string digital-to-analog converter (DAC) comprises least significant bits (LSB subword) interpolation circuitry. The LSB subword interpolation circuitry defines, for each input digital word (or code), an offset voltage representative of an M bit LSB subword of the input digital word. The offset voltage modifies a coarse analog representation voltage of an N bit most significant bits (MSB subword) of the input digital word. The LSB subword interpolation circuitry includes a coarse analog representative voltage input, an LSB subword input, an LSB modification circuit, an offset voltage defining circuit, and a summation device. The DAC further includes a segmented string and a coarse level device connected to tap points of the segmented string. The offset voltage defining circuit receives an LSB subword and defines an offset voltage for modifying the corresponding coarse analog representative voltage. Such an offset voltage is defined based on a given modified LSB subword.

Abstract: A switch capacitor amplifier using a “bottom plate sampling” type arrangement in the feedback network to mitigate the reduction in linearity due to feedback switch charge injection. The switch (18A) connecting the feedback capacitor (Cf) to the opamp (15) input is opened prior to the switch (19A) connecting the feedback capacitor (Cf) to the output such that the charge injected into the opamp input nodes come from the switch connected to the opamp input, and is independent of the signal value to the first order as the switches are at the opamp input common mode voltage.