Abstract: A drain-extended MOS transistor in a semiconductor wafer (300) of a first conductivity type comprises a first well (315) of the first conductivity type, operable as the extension of the transistor drain (305) of the first conductivity type, and covered by a first insulator (312) having a first thickness, and further a second well (302) of the opposite conductivity type, intended to contain the transistor source (304) of the first conductivity type, and covered by a second insulator (311) thinner than said first insulator (312). First and second wells form a junction (330) that terminates (320, 321) at the second insulator. The first well has a region (360) in the proximity of the junction termination, which has a higher doping concentration than the remainder of the first well and extends not deeper than the first insulator thickness.

Abstract: A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.

Abstract: A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304), its source (304b) and its gate (304c) connected to ground potential and its drain (304a) connected to the I/O pad. A well of the opposite conductivity type, partially separated from the substrate by shallow trench isolations, has a diode (302), its anode (302b) connected to the pad and also to the transistor drain, and its cathode (302a) connected to power 303). These transistor and diode connections create a parasitic silicon controlled rectifier (SCR) with the SCR-anode (310a) formed by the diode anode, the first base region formed by the well, the second base region formed by the substrate, and the SCR-cathode (311a) formed by the transistor source. The SCR structure provides a significantly lower clamping voltage and an about two times higher failure current than a substrate-pumped MOS transistor.

Abstract: A die mold machine for molding a plurality of semiconductor assemblies on multiple substrate/leadframes includes a plurality of die mold layers stacked vertically one above the other to form a plurality of die mold sections. The top die mold layer has at least one aperture or die hall in the top most die layer and apertures or die halls in the in-between layers for passing molding compound which flows through the die hall in the top layer down through the die halls or apertures between the die mold layers into the die mold sections for molding semiconductor assemblies on said substrate/leadframes between said die mold layers.

Abstract: This patent disclosure describes an effective synchronization technique for an embedded signaling system based on direct sequence spread spectrum technology. The technique provides an approach to robust detection of information codes embedded in an audio signal which is subject to undergoing such processes as re-recording of the material onto a different media, and conversions from digital to analog form and from analog to digital form. The technique is useful in preventing the embedded information from being corrupted or obscured by pirates via signal distortion operations including D/A and A/D conversions or by legitimate users in artistic processing of the material. The technique according to one embodiment of the present invention includes obtaining a timing error estimate in the process of synchronization by estimating the initial sampling rate/timing error by peak picking and by restoring the correct timing by sample interpolation after synchronization.

Abstract: For a leadframe for use with integrated circuit chips, a continuous strip of sheet-like base metal is pre-plated with a layer of nickel fully covering the base metal, further on one surface with a palladium layer in a thickness suitable for bonding wire attachment, and on the opposite surface with a layer of either palladium or lead-free solder in a thickness suitable for parts attachment. The leadframe structure is then stamped from the sheet so that the base metal is exposed at the stamped edges, enhancing adhesion to molding compounds.

Abstract: The semiconductor memory device has a memory capacity that can be increased without increasing the load to bit lines and has increased access speed. Because the output lines of bit line selector circuits 20 through 27 are precharged by charge circuits 30 through 37, and selectable bit lines (SBL, SBLZ) reach a high level before access is gained for reading from memory cells, data read previously is held unchanged for output signal SAOUT of data latch circuit 70. Because output lines of bit line selector circuits 20 through 27 are all at the high level even when another gate circuit becomes conductive as a new read address is set, the selected bit lines remains at the high level, and data previously read is held unchanged for output signal SAOUT of data latch circuit 70. Output signal SAOUT of data latch circuit 70 is changed to the next data read as soon as differential amplification operation of the bit lines is completed by amplifier circuits 40 through 47.

Abstract: Emulation communications via a test access port and boundary-scan architecture providing serial access to a serial connection of a plurality of registers disposed in a plurality of modules. One of the modules is selected for communication. Nonselected modules are made nonresponsive to data on the serial connection. The external emulation hardware supplies a serial signal having a first logic state for a number of cycles greater in number than a number of bits of the serial connection of registers to the test access port. The emulation hardware supplies a start bit having an opposite logic state. The selected module detects the start bit and stores the next predetermined number of data bits. These bits could be data bits to be stored in a program visible data register or bits interpreted as an instruction for execution by the module. The selected module may transmit return communications via the serial scan path using the same format.

Abstract: Pipeline activity information associated with all stages of execution of an instruction in an instruction pipeline of a data processor is presented to an event detector in timewise aligned format. This permits events in the pipeline to be presented to the event detector in a sequence that is consistent with the context in which a programmer of the event detector would normally think of those events, thereby simplifying programmation of the event detector.

Abstract: An embodiment of the instant invention is a method of oxidizing a first feature (feature 108 and/or feature 104 of FIG. 1 and feature 314 of FIG. 3) while leaving a second feature substantially unoxidized (features 110 and 112 of FIG. 1 and features 310 and 312 of FIG. 3), the method comprised of subjecting the first and second features to an oxygen-containing gas and a separate hydrogen-containing gas. Preferably, the oxygen-containing gas is comprised of gas selected from the group consisting of O2, N2O, CO2, H2O, and any combination thereof, and the hydrogen-containing gas is comprised of H2. The first feature is, preferably, comprised of polycrystalline silicon, silicon oxide, or a dielectric material, and the second feature is, preferably, comprised of tungsten.

Abstract: An embodiment of the invention is a method of manufacturing a semiconductor wafer 2 where a layer of undoped silicon glass 15 is formed over the front-end structure 3. Another embodiment of the present invention is an integrated circuit 2 having a back-end structure 4 in which the dielectric layer 15 contains undoped silicon glass.

Abstract: A system (25) for detecting defects in a semiconductor wafer (10), such defects including voids (V) present in metal conductors (2, 4) and plugs (7), is disclosed. An x-ray source (20) irradiates the wafer (10) through a first aperture array (24) having openings (26); a second aperture array (28) is located on the opposite side of the wafer (10) from the source (20), and has openings (30) that are aligned and registered with the openings (26) in the first aperture array (24). An array of x-ray detectors (31) is located adjacent to the second aperture array (28), with each detector (31) associated with one of the openings (30) of the second aperture array (28). The detectors (31) communicate signals regarding the magnitude of x-ray energy that is transmitted through wafer (10) at locations defined by the openings (26, 30) through aperture arrays (24, 28), to an analysis computer (34). A wafer translation system (32) indexes or otherwise moves the wafer (10) between the aperture arrays (24, 28).

Abstract: Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular semiconductor island (102). Each island contains three parallel regions of the opposite conductivity type: the center region (104) is operable as the transistor drain and the two other regions (103 and 105), abutting the isolations, are operable as transistor sources. Transistor gates (106 and 107) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts (108) are placed on both source regions and the drain region. The source contacts are placed so that the spacing (120) between each contact and its respective isolation is at least twice as large as the spacing (121) between each contact and the gate.

Abstract: In a microprocessor, a method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: A data processing system is provided with a digital signal processor which has an instruction for conditionally branching based on the contents of a specified test register. Each time a branch is taken, the register is decremented as a side effect of executing the branch instruction. In addition, a predicate register is specified by the instruction. A branch occurs only if both registers meet specified conditions.

Abstract: A method of predicting the effect of blob test in GSP sample testing is disclosed.

Abstract: A system for signal boosting includes a capacitance boosting component that contains a first and second transistor and a capacitor, wherein a positive terminal of the capacitor is electrically connected to a drain of the second transistor and a negative terminal of the capacitor is electrically connected to a source of the first transistor. The system also includes a third transistor operable to receive a clock signal. A drain of the third transistor is electrically connected to the positive terminal of the capacitor. A fourth transistor is operable to receive an inverse of the clock signal. A drain of the fourth transistor is electrically connected to the positive terminal of the capacitor. The system further includes a boost component electrically connected to the capacitance boosting component wherein an output of the boost component is within a selected boost voltage range.

Abstract: A multiple block adder is provided wherein carry select adder (CSA) is used in the most significant bit (MSB) block, a carry increment adder (CIA) is used in the least significant bit block and a combination of carry increment adder (CIA) and carry lookahead adder (CLA) circuit is used in the middle block.

Abstract: Semiconductor device fabrication methods are provided in which a carbon-containing region is formed in a wafer to inhibit diffusion of dopants during fabrication. Front-end thermal processing operations, such as oxidation and/or anneal processes, are performed at high temperatures for short durations in order to mitigate out-diffusion of carbon from the carbon-containing region, such that carbon remains to inhibit or mitigate dopant diffusion.