Abstract: An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits.

Abstract: A number of basic equalization and demodulation structures have been shown to be appropriate for DMT systems depending on the channel, noise, and system parameters. These include single path, dual path, oversampled, and double rate structures. Using the fundamental computation units of two TEQs (FIR filters) and two FFTs, in conjunction with simple delays, downsampling and routing, single path, dual path, oversampled and double rate equalization structures can be realized from a common equalization structure.

Abstract: Operational amplifier circuits (20, 30) including error capacitors (C3, C13) for storing finite gain effect error voltages for correction of output voltages of the circuits (20, 30), are disclosed. The circuits (20, 30) are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (15, 25), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter (50) using the disclosed operational amplifier circuits (20, 30) is also disclosed.

Abstract: An apparatus for controlling operation of a processor device during startup of the processor device includes: (a) a signal treating circuit receiving a voltage supply signal at a voltage supply locus; the signal treating circuit using the voltage supply signal for generating a first treated signal and a second treated signal; and (b) an output circuit coupled with the signal treating circuit; the output circuit receiving the first treated signal and the second treated signal and generating a control signal at an output locus based upon a relationship between the first treated signal and the second treated signal; the output locus being coupled with the processor device; the control signal effecting the controlling.

Abstract: An evaluator (210) having an input (207) for receiving a signal indicative of a channel current sensed via a sensor in a mutlichannel current sharing system, and circuitry (313, 319) coupled to the input (207) and responsive to the signal for indicating an unreliable sensing for the sensor when a low current condition occurs for a time period exceeding the switching time period of the channel current. Further, the apparatus can include an additional input (207) and circuitry (313, 319) for evaluating an additional sensor sensing an additional channel current. The low current condition is characterized by thresholds corresponding to the peak level and a valley level of the channel current over a switching time period.

Abstract: A voltage-to-current conversion circuit includes an error amplifier (12A) which amplifies a voltage difference between the drains of the first (6) and second (7) transistors of a first current mirror, wherein drain current of the first transistor is proportional to an input voltage (Vin). The output of the error amplifier is connected to the gates of the first and second transistors. A compensation capacitor is coupled between the gate and drain of the first transistor. The drain current of the second transistor flows through a cascode transistor (16) to an input of a second current mirror, an output transistor (31) of which provides a current (Ibias) which is proportional to the input voltage (Vin) as a bias current for the error amplifier, to provide stable operation.

Abstract: A controller area network transceiver and a transmission method for a controller area network provides improved symmetry between its differential output signal CANH and CANL such that capacitive imbalance is minimized. The transceiver disclosed herein includes a driver including a non-inverted output that couples to the first output terminal CANH and a inverted output that couples to the second output terminal CANL. A receiver comparator includes a non-inverted input coupled to the first output terminal CANH and a inverted input coupled to the second output terminal CANL. A first and second impedance matching circuit portions capacitively balance the first and second output terminals such that efficient common-mode rejection is enabled by setting the RC time constants formed by each impedance matching circuit and external resistances to be substantially equivalent.

Abstract: A method for generating a representation of a particular signal among video signals representing a display, the signals including a first component having a first bandwidth and a second component having a smaller second bandwidth, includes the steps of: (a) measuring first samples of the first component outside the second bandwidth for an interval in each signal; (b)measuring second samples of the second component inside the second bandwidth for the interval; (c) establishing factors based upon first samples; (d) establishing filter modes based upon second samples; (e) establishing a correlation between factors and filter modes; (f) filtering the signals using a selected filter mode; (g) identifying a selected factor according to the correlation for the selected filter mode; (h) employing the selected factor for weighted mixing of the samples to generate the representation for the time interval; and (g) repeating steps (a) through (h) until the representation is completed.

Abstract: An aspect of the present invention reduces the effect of any noise present along with an input signal when sampling the input signal by charging each of several parallel connected capacitors for different time durations with at least some non-overlap. In an embodiment, such an approach is used in a switched capacitor amplifier circuit of an ADC. The capacitors in that embodiment start charging at the same time instance, but stop charging at different time instances due to the design of associated switches and control signals.

Abstract: Disclosed are methods and circuits for impedance-controlled write drivers using matched impedance control circuits coupled in parallel with a magnetic write head.

Abstract: An integrated circuit for use with an external Hall sensor that permits to at least substantially cancel out the temperature drifts of the Hall sensor, as caused by the temperature drift of the current supplied to the Hall sensor, and the gain of the Sigma-Delta modulator. Specifically, the circuit provides an integrated circuit for use with an external Hall sensor, that has an analog input for application of a Hall voltage from the Hall sensor, a digital data output and a current output for connection to a current input of the Hall sensor. The integrated circuit comprises a Sigma-Delta modulator with an input connected to the analog input and an output connected to the digital data output. An internal reference voltage source is also included in the integrated circuit, and an internal current source is connected to the current output for the Hall sensor.

Abstract: An apparatus, method and system for retracting a read/write head (13) to a landing position of a disk (11) in a disk drive system (10) which includes an actuator (33) coupled with the head (13) for retracting in a first direction toward an outside diameter of the disk (11) and a second direction toward an inside diameter of the disk (11) in response to corresponding signals. A control device (32) coupled with the actuator (33) which is adapted for determining a retract direction for the read/write head (13), wherein a first signal indicative of a first direction and a second signal indicative of a second direction is provided to the actuator (33), the control device (32) further providing the first signal following a loss of power which energizes the disk drive motor (38) of the disk drive system and providing the second signal subsequent to providing the first signal for retracting the read/write head (13) to the landing position.

Abstract: A capability predictor that comprises a database 15 of capability of multiple designs is disclosed. The process capability data includes costs, quality, cycle time, and performance models. The process owner (expert) provides the data. The developer inputs equations necessary to calculate the predictions based in the selected design characteristics and the user selects the design. A processor 11 calculates the prediction based on the selected design and a display, such as monitor 11a or printer 16, displays the results of the predictions.

Abstract: A digital signal system (50) determines an approximate antilog x from a value of ƒ(x), where x has a base b.

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (102), forming a dielectric layer (104) over the semiconductor substrate (102), and etching a trench structure (106) or a via structure (106) in the dielectric layer (104) to expose a portion of a surface of the semiconductor substrate (102). The method also includes the steps of treating a surface (104a) of the dielectric layer (104) with an adhesion solution, such as a reactive plasma including hydrogen, and forming a diffusion barrier layer (110) over the dielectric layer (104). Moreover, the adhesion solution chemically interacts with the surface (104a) of the dielectric layer (104) and enhances or increases adhesion between dielectric layer (104) and diffusion barrier layer (110).

Abstract: An apparatus for controlling output signals at an output locus of a power converting device has a rectifier coupled to receive an input signal and present a rectified input signal for switching connection with one of a first and a second network. The first network includes the rectifier. The second network includes part of the first network and the output locus. The networks establish a return current to the rectifier. The apparatus includes: (a) a current indicating unit coupled with the output locus for combining an extant output signal with a time-integrated signal to present a calculated current signal; and (b) a comparing unit coupled with the first network and the current indicating unit for receiving the return current. The comparing unit drives the switching connection when the calculated current signal and the return current have a predetermined relationship.

Abstract: A small vocabulary speech recognizer suitable for implementation on a 16-bit fixed-point DSP is described. The input speech xt is sampled at analog-to-digital (A/D) converter 11 and the digital samples are applied to MFCC (Mel-scaled cepstrum coefficients) front end processing 13. For robustness to background noises, PMC (parallel model combination) 15 is integrated. The MFCC and Gaussian mean vectors are applied to PMC 15. The MFCC and PMC provide speech features extracted in noise and this is used to modify the HMMs. The noise adapted HMMs excluding mean vectors are applied to the search procedure to recognize the grammar. A method of computing MFCC comprises the steps of: performing dynamic Q-point computation for the preemphasis, Hamming Window, FFT, complex FFT to power spectrum and Mel scale power spectrum into filter bank steps, a log filter bank step and after the log filter bank step performing fixed Q-point computation. A polynomial fit is used to compute log2 in the log filter bank step.

Abstract: A controller providing increased control with lesser final error for an actuator when there is a force accelerating the actuator, such as at the end of travel during a retract operation. An extension of the integrator may be provided for implementing a second direction to integrate a final error. One embodiment of the invention may comprise a counter and an analog multiplexer controlling the attenuation of the command voltage.

Abstract: A fan control system and method that maintains the operating temperature of computer and electronic devices or components at about a predetermined control level to minimize power consumption and audible noise. The fan control system is a programmable closed loop system including a temperature sensor, first and second fan controllers, and a fan/motor assembly including a power converter, a motor, and a fan. The first fan controller provides programmable acceleration/deceleration of the fan during an initial fan spin up, and the second fan controller runs the fan only as fast as necessary to keep the sensed temperature level of a computer device as close as possible to the predetermined control level, thereby minimizing the power consumption of the system and the audible noise of the fan.