Abstract: An off-line partial wafer scanner system is disclosed that resolves partial wafermap related issues that result holt-lot in semiconductor assembly. The system eliminates the need to teach locator die at die attach (die bonder) machine. The reaching of partial map locator die is done in die interface areas instead of at the die bonder machine. This resolves the die quantity discrepancies issue, die bonder operator error and missing locator die information due to error made at the die bonder. An image-processing algorithm is employed to achieve reliable off-line locator die teaching system. In partial wafermap processing, the locator die is recognized by utilizing a vision system. A production operator records the wafer identification, and quarter or halves the wafer using a saw machine. The production operator scans the first quarter Q1 or first half H1 with a scanner and determines the locator die location as well as exact quantity of dies.

Abstract: An equipment (400) for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator (401) and an on/off switch relay (403). The relay is resistively connected by a first resistor (402) to the generator and by a second resistor (404) to the socket (405a) for the device-under-test (406); the relay is operable in a partially ionized ambient. A capacitor (407) is connected to the relay, to the generator, and to the device, and is operable to discharge high energy pulses through the device. A third resistor (410) is in parallel with the capacitor and the device, and is operable to suppress spurious pulses generated by the relay. This third resistor has a value between about 1 k? and 1 M?, preferably about 10 k?, several orders of magnitude greater than the on-resistance of the device-under-test.

Abstract: Electrostatic discharge protection devices formed at a face of a semiconductor substrate, integrated with a component sensitive to electrostatic discharge, wherein the protection device is interdigitated with the component. The invention is applicable to many kinds of components, for example to a noise-decoupling capacitor shaped as an nMOS transistor with thin dielectric, or to an input buffer shaped as an nMOS transistor, or to an antenna shaped as an nMOS transistor. The protection device includes an nMOS transistor. The insulator of the gates, preferably silicon dioxide, is thin and in need of protection against ESD damage. The interdigitation may be configured in one or more planes. Further, the protection device may lie in a single plane spaced apart from the plane defined by the components. The protection device may also partially be merged with the component.

Abstract: A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination.

Abstract: A method and system for dynamically linked emulation with a mix of target debuggers on a host computer wherein a debugger for each processor on the target system connects to a target interface for that kind of processor. That target interface then communicates with an emulator dynamic loader on the host computer connected to an emulator. The target interface communicates with the dynamic loader on the host computer to determine if there is support for the desired kind on the emulator. If not a target interface is loaded to the emulator and connected to the already running software on the host. A connection to this target interface software on the emulator is then provided to the host computer.

Abstract: A method of blind assembly processing a wafer by pick and place equipment is described. This method includes determining the wafer diameter or radius and determining the bad die edge exclusive zone. This determined diameter or radius and the determined edge exclusive zone is used to make a black paper mask and place it over the wafer or to cut or saw away from the wafer the bad die edge exclusive zone. This enables the pick and place equipment to avoid the bad dies in the bad die edge exclusive zone.

Abstract: The present invention provides a method for far branch and call instructions. The present invention includes the link-time modification of object code generated by the compiler or assembler and the addition of custom generated object code to the link for the purpose of implementing far branches and calls without changing the compiler generated instructions or expanding compiler generated object code.

Abstract: A method of generating profiled optimized code using user interface (17) that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided. A program (11) is compiled in a compiler (13) with two or more compiler options such as size and speed and the resulting executables (14) are profiled (15). The results of the profiles (19) are analyed in a solver (21) for generating sets of useful solutions (23) wherein the sets have methods of compiling at the function level. The useful solutions (23) are displayed (18) at the user interface (17) to allow the user to visually understand, inspect and manipulate compiler options to select compiler options (13a) for the program.

Abstract: A semiconductor device (700) having a leadframe with a first plurality of segments (110) having a narrow end portion (111) in a first horizontal plane (211) and a wide end portion (112) in a second horizontal plane (212). The leadframe further includes a second plurality of segments (120) having a narrow center portion (121) in the first horizontal plane, at least one wide center portion (122) in the second horizontal plane, and narrow end portions (123) in a third horizontal plane (213), which is located between the first and second planes.

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract: A phase-locked loop is provided which is operable to lock the sampling clock (pixel clock) to the incoming horizontal sync pulse contained within composite video information. Given the input signal is a VCR signal or a normal noise-free signal, there exists two modes of operation, coarse lock mode and fine lock mode, which are used in controlling the phase-locked loop. In the coarse lock mode, coarse corrections are made to a horizontal discrete time oscillator so that a fast lock may be achieve using the fine lock mode. Coarse corrections are based on a normalized sum of weighted pixels collected within a narrow gate window. Lock is achieved when the falling edge is centered within the window. Given the input signal is a television signal having noise, there exists one mode of operation where the flat window phase detector is used instead of coarse lock mode to bring the sync edge to fall within the window, where the flat window normalization constant is tuned.

Abstract: A method and system for calibration of a data acquisition path is achieved by applying a voice utterance to a first high quality microphone and reference path and to a test acquisition path including a test microphone such as a lower quality one used in a car. The calibration device includes detecting the power density of the reference signal YR through the reference path and detecting the power density of the signal YN through the acquisition path. A processor processes these signals to provide an output signal representing a noise estimate and channel estimate. The processing uses equation derived by modeling convolutive and additive noise as polynomials with different orders and estimating model parameters using maximum likelihood criterion and simultaneously solving linear equations for the different orders.

Abstract: Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry (101) on a substrate (106) that discharges an ESD pulse to the integrated circuit to ground (104a). The protection circuitry (100) also includes a drive circuitry (102) that uses a portion of the ESD pulse voltage to bias the substrate (106) using a first guard ring (110) in the substrate (106), which surrounds the discharge circuitry (101) and drive circuitry (102). The protection circuitry (100) further includes a second guard ring (120) in substrate (106), which surrounds the first guard ring (110) and connects to Vss/ground potential (104c), thereby providing uniformity of the substrate bias.

Abstract: A multi-channel acoustic cancellation system 40 with, for example, stereo speakers and a pair of microphones in the transmitting and receiving rooms (11 and 21) has time varying all-pass filters (45, 47) in the signal path between the microphones (13, 15) in the transmitting room (11) and the speakers (27, 29) in the receiving room (21) to provide decorrelation.

Abstract: A new method for quantization of the LPC coefficients in a speech coder includes a new weighted error measure including every frame sampling an impulse response from LPC filter 21 of said coder, filtering the samples using a perceptual weighting filter 39 and processing in a computer 39 to calculate autocorrelation function of the weighted impulse response, computing Jacobian matrix for LSF (Line Spectral Frequency), computing correlation of rows of Jacobian matrix and calculating LSF weights by multiplying correlation matrices.

Abstract: The present invention provides a visual linker. The visual linker includes a link server that implements linking instructions for sections to a memory. The visual linker also includes a graphical user interface that receives said instructions and displays said sections within said memory. The visual linker also includes an application programming interface that receives said instructions and reports the results of said linking instruction and said sections within said memory. The visual linker also includes an incomplete link comprising sections not allocated to said memory. The visual linker also includes a link recipe comprising said instructions implemented by said link server.

Abstract: On the surface of a semiconductor material of a first conductivity type 101a, a lateral MOS transistor 100 is described surrounded by a well 171 of the opposite conductivity type and, nested within the well, an electrical isolation region 102. The semiconductor region 101a embedding this transistor has a resistivity higher than the remainder of the semiconductor material 101 and further contains a buried layer 160 of the opposite conductivity type. This layer 160 extends laterally to the wells 171, thereby electrically isolating the near-surface portion of the semiconductor region from the remainder of the semiconductor material, and enabling the MOS transistor to operate as an electrically isolated high-voltage I/O transistor for circuit noise reduction, while having low drain junction capacitance. In the first embodiment of the invention (FIG.

Abstract: An algorithm and handheld device adapted to select a subexpression of a mathematical expression. An expression string of the handheld device is selected, and the expression string is converted to a contiguous tokenized Polish representation (CTPR) of the expression, and the CTPR of the expression is loaded into an n-ary tree. The user may navigate the visual representation of the expression to select a subexpression. The handheld device is adapted to select the subexpression from the n-ary tree.

Abstract: A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the sample parameters are measured and if the die passes the sample parameters the die is good and repeat the steps of determining if the die is within specification and measuring the sample parameters until a die fails the measurement test or requires a trimming and if a die fails a measurement test or requires trimming perform 100 percent test and trim.

Abstract: A die mold machine for molding a plurality of semiconductor assemblies on multiple substrate/leadframes includes a plurality of die mold layers stacked vertically one above the other to form a plurality of die mold sections. The top die mold layer has at least one aperture or die hall in the top most die layer and apertures or die halls in the in-between layers for passing molding compound which flows through the die hall in the top layer down through the die halls or apertures between the die mold layers into the die mold sections for molding semiconductor assemblies on said substrate/leadframes between said die mold layers.