Abstract: A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid-rail value for tri-state detection, and with less dependence on variations in product, process and temperature. In accordance with an exemplary embodiment, an exemplary tri-value decoder circuit comprises a switch circuit, a feedback loop and a sequence detector. An exemplary switch circuit is configured to facilitate sampling of a tri-state input signal through control by the feedback loop, with the sequence detector configured for decoding the tri-state input signal into a two-bit digital signal by detecting at least two samples of the tri-state input signal during a sampling period.

Abstract: Disclosed herein are methods and systems for sensing and controlling the temperature of a resistive element configured for use in a read/write head of a magnetic data storage device. In one embodiment, a method includes detecting a voltage across the resistive element, where the voltage varies as a function of a temperature of the resistive element. The method also includes comparing the voltage to a predetermined value to determine a variation of the voltage from the predetermined value, and then altering a power applied to the resistive element based on the variation. In this exemplary embodiment, the temperature of the resistive element is then controlled as a function of the altered applied power.

Abstract: A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more external devices. The interface accomplishes this function by serializing bus transactions in one device, transferring the serial transaction between devices via one interface port, and de-serializing the transaction in the external device. The general features include low pin count (as few as three signals), simple packet based transfer protocol for memory mapped access, symmetric operation, simple block code formatting, supports both host to peripheral and peer to peer transactions, and support multiple outstanding transactions.

Abstract: A first downlink transmission beam and a second downlink transmission beam is determined based on a received user-derived signal. The first downlink transmission beam is substantially uncorrelated with the second downlink transmission beam. The first downlink transmission beam is associated with a portion within a first sector. The second downlink transmission beam is associated with a portion within a second sector. A first signal is diversity encoded to produce a first diversity-encoded signal. A second signal is diversity encoded to produce a second diversity-encoded signal. The first diversity-encoded signal is sent over the first downlink transmission beam. The second diversity-encoded signal is sent over the second downlink transmission beam.

Abstract: A write driver output circuit having a programmable output impedance. A plurality of amplifiers are disposed in parallel between an input and an output of an impedance matching section of the write driver circuit and can be selectively enabled to correspondingly set the output impedance of the write driver circuit. The amplifiers may be Class AB amplifiers, each of which have a smaller size than an conventional AB used in a single amplifier write driver circuit. Each of the Class AB amplifiers has a corresponding matching resistor, and a current source, each being selectively enabled and disabled by enabling and disabling, respectively, the corresponding current sources, such as through the use of serial interface bits.

Abstract: A class-AB output stage circuit is configured with controllable reference voltages for providing stable quiescent current. An exemplary output stage circuit comprises one or more control circuits, such as feedback loops, configured to control and/or adjust the reference voltages within the class-AB circuit based on the output voltage and/or supply rail voltage levels. In addition, an exemplary output stage circuit can also comprise one or more clamp circuits configured to facilitate operation of the output stage circuit when the output supply is proximate to or exceeds a positive or a negative supply rail.

Abstract: An amplifier apparatus includes: (a) an integrator having an input for receiving an input signal, and integrating the input signal to present an integrated signal; (b) a first comparer coupled with the integrator for comparing the integrated signal with a varying reference signal to produce an output signal; and (c) a feedback circuit, coupled to receive the integrated signal and coupled with the input structure, that includes: (1) a second comparer coupled for receiving the integrated signal and comparing the integrated signal with a reference level related to the reference signal; the second comparer presents an actuating signal when the integrated signal has a predetermined relationship with the reference level; and (2) a switch coupled with the second comparer unit and with the input and responding to the actuating signal to affect the input signal appropriately to reduce the integrated signal when the actuating signal is at a predetermined level.

Abstract: An improved charge pump circuit that is capable of producing a constant output current. The charge pump circuit includes a controllable current source, at least one switching element coupled between the controllable current source and an output node, and a load capacitor coupled between the output node and ground potential. The switching element switches in response to an input signal to allow current pulses to flow from the controllable current source through the output node. The load capacitor operates as an integrator to convert the output current pulses into a voltage level. The controllable current source provides increased current levels as the output voltage level of the charge pump increases, thereby enhancing the overall efficiency of the charge pump circuit.

Abstract: A new iterative hierarchical linear regression method for generating a set of linear transforms to adapt HMM speech models to a new environment for improved speech recognition is disclosed. The method determines a new set of linear transforms at an iterative step by Estimate-Maximize (EM) estimation, and then combines the new set of linear transforms with the prior set of linear transforms to form a new merged set of linear transforms. An iterative step may include realignment of adaptation speech data to the adapted HMM models to further improve speech recognition performance.

Abstract: A switched capacitor environment in which a feedback capacitor of a stage is flipped to be used as a sampling capacitor of the next stage. Due to such use of the feedback capacitor, the noise introduced by the stages is substantially reduced. Such switched capacitors can be used in analog to digital converters (ADC).

Abstract: The temperature of an internally or remotely sensed diode is determined using sequential currents applied to the diode, while compensating for parasitic resistance effects on the sensed diode so that the temperature indication is accurate. A method or circuit is provided which isolates the parasitic resistance value itself or a voltage representative of the parasitic resistance, so that an error compensation value can be obtained for use in subsequent measurements.

Abstract: A typical English pronunciation dictionary takes up to 1,826,302 bytes in ASCII to store. A five times compression while maintaining computability is achieved by prefix delta encoding of the word and error encoding of the pronunciation.

Abstract: A GTL output structure having an active charging and discharging stage that actively restores internal nodes for slew rate control without the need to wait for a slow rise and fall RC time constant is disclosed herein. The novel GTL output structure includes an input stage connected to an RC network for providing slew rate control. The output stage connects between the RC network and a feedback network. The feedback network in includes an active charging stage for providing a charging current to the gate of the at least one transistor for a period of time to the value of a power supply rail and wherein the feedback network includes an active discharging stage for providing a discharge current from the gate of the at least one transistor to ground.

Abstract: Method for assembling a semiconductor device having fatigue-resistant interconnection fillet provides a semiconductor chip with at least one solder bump comprising an alloy of tin and lead with a melting temperature higher than the solder paste used. Further, a solder paste (preferably binary) is provided, which comprises tin and about 2.5 weight percent silver, and has a melting temperature of about 221° C. The solder bump is brought in contact with the solder paste, the bump is partially immersed in the paste, and thermal energy is supplied to reflow the solder paste at about 235° C. The amount of energy and time after the reflow of the paste is controlled so that the molten paste dissolves a pre-determined amount of the solder bump (lead and tin) to form a ternary alloy of about eutectic composition (about 1.62 weight % Ag, 36.95 weight % Pb, 61.43 weight % Sn) without melting the solder bump.

Abstract: A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

Abstract: The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.

Abstract: A preamplifier device (26) for a thin film transducer disk drive system having operation speeds up to and greater than 2 Gb/s. The device (26) includes a low power/high speed driver (203) having a cascaded Class AB buffer. In at least one embodiment the device (26) includes separated drive devices in the driver (203) and H-bridge circuit (205) realized in multiple smaller devices biased separately to reduce transistor self-heating effects and a further embodiment includes a reference (201) having a base cancellation scheme and a Class AB current source for improving accuracy and stability is such high speed devices.

Abstract: An audio preamplifier (10) based on an operational transconductance amplifier, in combination with a class D audio output amplifier (12) is disclosed. The input signal is coupled to the preamplifier (10) through a capacitor (14) in series with a resistor (17) that sets the transconductance of the preamplifier. The preamplifier (10) includes a differential operational amplifier (20) that drives output MOS transistors (22a, 22b), which are biased by current sources (24a, 26a; 24b, 26b). Feedback from the drain nodes of the output MOS transistors (22a, 22b) to the inputs of the differential operational amplifier (20), along with the series capacitor (14) and resistor (17) input coupling, ensures minimum offset voltage and current at the output of the preamplifier (10). Common mode feedback control amplifiers (25, 29) ensure proper bias of the components into the saturation region.

Abstract: Operational amplifier circuits (20, 30) including error capacitors (C3, C13) for storing finite gain effect error voltages for correction of output voltages of the circuits (20, 30), are disclosed. The circuits (20, 30) are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (15, 25), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter (50) using the disclosed operational amplifier circuits (20, 30) is also disclosed.

Abstract: A write driver produces balanced voltages across head by using the input write data drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.