Abstract: Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

Abstract: A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.

Abstract: A substrate (110) for an unpackaged integrated circuit (IC) chip (118). The substrate comprises an insulative material (112), a plurality of contacts (114) disposed thereon, and a conductive ring (150) disposed around the outer perimeter of the contacts (114). Conductive traces (115) may be disposed around one or more contacts (114) and may be coupled to the conductive ring (150). An electro-less plating technique is utilized to plate contacts (114), avoiding unnecessary conductive material such as plating stubs being included in the contact (114) pattern, reducing interference. The conductive ring (150) shields the chip (118) from interference.

Abstract: A combined channel and entropy decoder is provided that achieves a significant bit-error rate improvement using likelihood values (61) instead of conventional bits. The likelihood values are stored in a buffer (62). A unique code-word is searched in the bit pattern or in the likelihood value. When a unique code-word is found at the identifier (63), candidate code-words are loaded into computation units where each unit computes code-word likelihood for a given code-word bit pattern. The code-word likelihood values are compared and the selected code information is fed back to the code-word controller 67 to proceed to the next-step decoding.

Abstract: Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, write address, and read data and read address to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. Simultaneously read and write to a single node is prohibited. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data and of incoming write data. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Abstract: A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting and measuring an output 15 of the self-timed sequential circuit 2.

Abstract: An operational amplifier circuit includes: a first differential pair 20 of a first conductivity type having a first current branch and a second current branch; a second differential pair 22 of a second conductivity type having a first current branch and a second current branch; a first current mirroring device MP11 and MP26 coupled between the first branch of the first differential pair 20 and the second branch of the second differential pair 22 for combining the currents from these two branches; and a second current mirroring device. MN22 and MN24 coupled between the first branch of the second differential pair 22 and the second branch of the first differential pair 20 for combining the currents from these two branches.

Abstract: A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a using instruction and inserting a NOP field into the defining or using instruction. When inserted into the load instruction, the NOP field defines the following latency following the load instruction. When inserted into the using instruction, the NOP field defines the latency preceding the using instruction. In addition, a method for reducing total code size during branching may include the steps of determining a latency following a branch instruction for initiating a branch from a first point to a second point in an instruction stream, and inserting a NOP field into the branch instruction.

Abstract: A method for extracting blanket (qual) polish rates from interferometry signals off patterned (product) wafer polish during non-enpointed CMP. The method includes estimating polish rates using polish data near the end of the polish period. Non-linear regression and iterative optimization is presented to extract relevant information. The processing includes least square processing step (43), determining the search fit (44) and determining if this is the best fit (45).

Abstract: After via etch, a low-k dielectric layer (104) is treated with an in-situ O2 plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.

Abstract: A surface plasmon resonance (SPR) sensor (10) is disclosed. The sensor (10) includes a light source (18) and polarizer (20), which emit polarized light toward a surface plasmon layer (22). Light is reflected from the surface plasmon layer (22) at many angles, toward a photodetector array (26) via a mirror surface (24). The surface plasmon layer (22) includes a resonance film (30), such as gold, and a hard protective layer (32). The hard protective layer (32) is of a thickness below the sensing range (R) of the SPR sensor (10), and protects the resonance film (30) from damage. Materials useful as the hard protective layer (32) include silicon carbide (SiC), diamond-like carbon (DLC), silicon dioxide, silicon nitride, titanium oxide, titanium nitride, aluminum oxide, aluminum nitride, beryllium oxide, and tantalum oxide.

Abstract: A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

Abstract: Using deuterium oxygen during stream oxidation forms an oxidizing vapor. Since deuterium is chemically similar to hydrogen, the oxidation process takes place normally and the silicon-silicon oxide interface is concurrently saturated with deuterium. Saturating the interface with deuterium reduces the interface trap density thereby reducing channel hot carrier degradation.

Abstract: A forward biased diode 40 is used to charge up a photodiode 26 rather than an NMOS transistor. This photodiode charging mechanism increases the dynamic range and optical response of active pixel arrays, and improves the scalability of the pixel element.

Abstract: A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.

Abstract: A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

Abstract: The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the capacitor 300 includes a first conductive plate 320 located over a semiconductor substrate 310, wherein the first conductive plate 320 has a second conductive plate 340 located thereover. The capacitor 300, in the same embodiment, further includes a dielectric layer 330 located between the first conductive plate 320 and the second conductive plate 340, wherein the dielectric layer 330 includes a Group 17 element.

Abstract: The laser driver circuit includes an array of differential pairs 50 and 52. Each one of the differential pairs is coupled to a corresponding tail current source 67 and 69. The total modulation current for the laser driver circuit is developed as the sum of the output current from the array of differential pairs 50 and 52. Each of the tail current sources 67 and 69 generates a subrange of the total range of modulation current. The tail current in a given differential pair will then only vary over a small subrange of the total modulation current range, and the device size in each pair may be optimized to keep the emitter current density near the level that gives optimum bandwidth. This is equivalent to electrically increasing the emitter area of the composite differential pair as the total modulation current is increased, keeping current density approximately constant at its optimal level.

Abstract: An original rectifier circuit is used to rectify an input signal and the input signal is coupled to be provided to a terminal of a amplifier. The amplifier is implemented to generate a differential output and the two terminals providing the differential output are coupled as inputs to a replica rectifier circuit, having electrical characteristics similar to the original rectifier circuit. One of the outputs of the amplifier provides a measure of the power of the input signal.

Abstract: The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again.