Abstract: A memory device including array (12) of memory cells (10) having an array voltage Vdd bussed such that the Vdd of columns are controlled independently. During a WRITE cycle, the Vdd of the addressed columns is lowered. Thereafter, the stability of the cell is reduced, and the cell (10) is advantageously more easily written. Cells in other columns in the addressed row remain at full Vdd and are more stable. Cells in un-addressed rows in the addressed columns will not have the access transistors turned on, and therefore will be more stable. With WRITE being facilitated with a lowered column Vdd, the cell is designed to be more stable than would otherwise have been possible while maintaining the ability to WRITE.

Abstract: A dynamic logic circuit (30). The dynamic logic circuit comprises a precharge node (30PN) to be precharged to a precharge voltage (VDD) during a precharge phase and a conditional discharge path (30L, 30DT) connected to the precharge node. The conditional discharge path is operable, during an evaluate phase, to conditionally couple the precharge node to a voltage different than the precharge voltage. The dynamic logic circuit also comprises an output (OUT3) for providing a signal in response to a state at the precharge node. Lastly, the dynamic logic circuit comprises voltage maintaining circuitry (30KT1, 30KT2), coupled to the output, for coupling the precharge voltage to the precharge node during a portion of an instance of the evaluate phase when the conditional discharge path is not enabled during the instance of the evaluate phase.

Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.

Abstract: A drive circuit, for example a gate line drive circuit for a TFT liquid-crystal display, having a circuit size smaller than in the past. A TFT drive circuit has the shifting direction of drive data sequentially shifted through shift registers (SR116-R60) and is further inverted by a control signal (SEL_SFT), and the data are shifted in the opposite direction, from the first shift register (SR61) to the second shift register (SR116). At this time, the upper group of switching circuits (SW1-SW56) or the lower group of switching circuits (SW116-SW61) is enabled and the other group is disabled by control signals (SEL_UP, SEL_LO). Once the drive data are shifted to the bits of the shift registers, a voltage selection signal generated by a decoder (DEn) is inputted to an output circuit via an effective switching circuit, and a drive signal for a TFT gate is outputted. The number of circuits is reduced because the shift registers (SR61-SR116) and decoders (DE61-DE116) are shared by two outputs.

Abstract: The invention describes a method for reducing the leakage current in thin gate dielectric MOS capacitors in integrated circuits. A bias voltage is determined for the MOS capacitor such that the capacitor area and leakage current constraints are satisfied. The MOS capacitor is not biased in inversion.

Abstract: An amplifier architecture using actively phase-matched feed-forward linearization includes: a first signal path having a scaling amplifier 40 in series with a main amplifier 42; a second signal path having a replica amplifier 44 in series with a correction amplifier 46; and a combining node 48 that combines the first signal path and the second signal path. This topology places the scaling amplifier 40 in the main signal path. By inverting the scaling factor from &bgr; to 1/&bgr;, this topology retains the distortion cancellation property while balancing the two signal paths. In this case the scaling amplifier 40 attenuates the input signal rather than amplifying it. The end result remains the same. The main amplifier output signal is lower than the replica amplifier's by a factor of &bgr;. This results in a third-order distortion component that is &bgr;3 times bigger at the replica amplifier output.

Abstract: A method for measuring a capacitance of a semiconductor is provided that includes positioning a measurement circuit in a scribe line area associated with the semiconductor. The scribe line area is indicative of a delineation that separates one or more portions of the semiconductor. A capacitance of one or more elements included within the one or more portions of the semiconductor is then measured using the measurement circuit. The method also includes comparing the capacitance measurement of the one or more elements included within the one or more portions of the semiconductor to a reference set of capacitance values such that a parameter associated with a manufacturing process that generated the semiconductor may be checked.

Abstract: A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Abstract: A variable-gain amplifier that prevents the change in the in-phase voltage of the output occurring when the gain is changed and improves the frequency characteristic compared with the conventional method. The differential current of currents I13 and I13′ changes corresponding to input signal S1. As a result, the differential current of currents I11 and I12 also change correspondingly, and the differential voltage v13 between nodes N1 and N2 varies. The gain of differential voltage v13 with respect to input signal S1 is variable corresponding to the current conversion gains of current converters 2 and 3. When the current conversion gains vary corresponding to the input signal S2, the voltages at nodes N1′ and N2′ are adjusted such that the voltages at nodes N1 and N2 are constant with respect to the change in gain.

Abstract: Image enhancement is automatically achieved by calibrating the reference voltage and gain of a differential amplifier and the integration interval so as to provide an input to a differential analog to digital converter (ADC) that utilizes the full dynamic range of the ADC. When used with a CMOS array, the imaging logic can be fabricated on a single chip with the array using combinational logic for fast, inexpensive calibration. Another advantageous feature is the ability to expand a desired portion of the luminance spectrum of the image in order to increase the digital resolution of the resulting image for that portion of the spectrum of interest.

Abstract: A digital system has at least one processor, with an associated multi-segment cache memory circuit. A single global validity circuit (VIG) is connected to the memory circuit and is operable to indicate if any segment of the multiple segments holds valid data. Block circuitry is operable to transfer data from a pre-selected region of the secondary memory to a particular segment of the plurality of segments and to assert the global valid bit at the completion of a block transfer. Direct memory access (DMA) circuitry is connected to the memory cache for transferring data between the memory cache and a selectable region of a secondary memory and is also operable to assert the global valid bit at the completion of a DMA block transfer.

Abstract: A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

Abstract: The pixels of an image sensor array can be readout (84, 85) in m×n blocks (m, n) that are compatible with the operation of a desired image compression algorithm (14), thereby reducing the amount of memory required by the image compression algorithm.

Abstract: A system for fabricating a mixed voltage integrated circuit is disclosed in which a gate is provided that contains a gate oxide and a gate conductor on a substrate. A first mask is deposited to pattern the length of the gate by etching, and a second mask pattern is deposited and used to etch the width of the gate, with or without a hard mask.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: The present invention discloses a polishing pad that can facilitate process stability, extend length of use, and mitigate process non-uniformity and process induced defects for chemical mechanical planarization processes. The polishing pad of the present invention is a composite of a top pad and a sealed sub-pad. The sealed sub-pad has a sealing mechanism that mitigates liquid penetration into the sub-pad thereby maintaining a substantially uniform compressibility of the sub-pad and the polishing pad and extending a useable life of the polishing pad.

Abstract: The image sensing device incorporates a charge multiplication function in its serial register. The design layout is compact in size and the charge multiplication register consists of multi-channel sections that are evenly positioned around the periphery of the image sensing area. The individual charge multiplying register sections are coupled together by only 90-degree multi-channel turns located at the image area array corners. The device allows for the optical image sensing area center to be located near the chip center and consequently near the mechanical package center with the minimum silicon chip area sacrifice.

Abstract: Correcting a mask pattern includes accessing a record associated with an uncorrected pattern that comprises segments. The record associates each segment with a correction grid of a number of correction grids, where each correction grid comprises points. A segment is selected, and an optimal correction for the segment is determined. A correction grid associated with the segment is determined. The segment is snapped to a subset of points of the associated correction grid, where the subset of points is proximate to the optimal correction, to form a corrected pattern of a mask pattern.

Abstract: A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.

Abstract: The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential is applied to the semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode will be partially or wholly formed with copper. Both the anode and the semiconductor will be exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolytes solution below 25° C. the rate of self annealing grain growth will increase reducing the final resistively of the copper lines.