Abstract: The formation of a one time programmable (OTP) transistor based electrically programmable read only memory (EPROM) cell (100) is disclosed. The cell (100) includes multiple concentric rings (108, 110) out of which gate structures are formed. An inner transistor based cell (130) formed from the inner ring (108) is shielded from isolation material (106) by one or more outer rings (110). The lack of overlap between the inner transistor and any isolation material promotes enhanced charge/data retention by mitigating high electric fields that may develop at such overlap regions (30, 32).

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: An integrated circuit thin film resistor structure includes a first dielectric layer (18A) disposed on a semiconductor layer (16), a first dummy fill layer (9A) disposed on the first dielectric layer (18B), a second dielectric layer (18C) disposed on the first dummy fill layer (9A), the second dielectric layer (18B) having a first planar surface (18-3), a first thin film resistor (2) disposed on the first planar surface (18-3) over the first dummy fill layer (9A). A first metal interconnect layer (22A,B) includes a first portion (22A) contacting a first head portion of the thin film resistor (2). A third dielectric layer (21) is disposed on the thin film resistor (2) and the first metal interconnect layer (22A,B). Preferably, the first thin film resistor (2) is symmetrically aligned with the first dummy fill layer (9A). In the described embodiments, the first dummy fill layer is composed of metal (integrated circuit metallization).

Abstract: The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.

Abstract: A sleep control system and method are provided that permit a reference clock and the direct sequence spread spectrum (DSSS) modem in a mobile station receiver to be turned off and turned back on at arbitrary points in time while still maintaining accurate base station system time. Accurate timing is made possible through a number of techniques including precise initial calibration using a rising edge/falling edge averaging system, determining the sleep clock and reference clock frequencies, and the determination of the frequency drift of the sleep clock that occurred during the previous sleep interval.

Abstract: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: The present invention provides a method of forming a metal seed layer 100. The method includes physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also includes a RF plasma etch of the seed metal 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the seed metal 200.

Abstract: A quantization circuit includes a plurality of resistors, a plurality of tap points, and a plurality of coarse comparators. Each coarse comparator has a first input coupled to an input voltage and a second input coupled to a corresponding coarse tap point voltage. Each coarse comparator operates during a first phase to produce a “1” only if the input voltage exceeds the corresponding coarse tap point voltage. A plurality of fine comparators each have a first input coupled to the input voltage, and each fine comparator operates during a second phase to produce a fine output level indicative of whether the input voltage exceeds a corresponding tap point voltage of a group of tap points located immediately below the tap point connected to the highest coarse comparator producing a “1”.

Abstract: A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.

Abstract: Methods (300, 400) are described for calibrating the implantation angle of an ion implanter utilized in the manufacture of semiconductor products. One method (300) includes implanting (330) phosphorous ions into a pilot wafer held by a wafer platen held at a starting implantation angle in the ion implanter. The phosphorous implantation into a p-doped substrate of the pilot or blank wafer, for example, forms a semiconductive sheet. The method (300) then includes changing the implantation angle (340), and implanting another wafer (330) with phosphorous ions. The angle changing (340) and implanting (330) of other wafers continues in this manner until all wafers or angles are implanted (350) as desired. The phosphorous implanted wafers are then measured (360) with a four-point probe, for example, to obtain the sheet resistance of all the implanted wafers.

Abstract: The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

Abstract: An amplifying circuit which may be useful in a diamond buffer amplifier or operational amplifier includes an input transistor including an emitter, a collector, and a base coupled to receive an input voltage. An adjustable current source circuit is coupled between a first reference voltage and the emitter of the input transistor. A current source is coupled between a second reference voltage and the collector of the input transistor. An isolation resistor has a first terminal coupled to an output terminal of the adjustable current source circuit and a second terminal coupled to the emitter of the input transistor. A current follower circuit is coupled between the collector of the input transistor and an input terminal of the adjustable current source circuit. A feed-forward capacitor is coupled between the collector of the input transistor and the first terminal of the isolation resistor.

Abstract: Amplifier circuitry includes an input stage having a transconductance stage including first and second input transistors and a first tail current source, gates of the first and second input transistors being coupled to first and second input signals, respectively. A bulk electrode capacitance driver includes third and fourth input transistors and first and second associated cascode transistors and a second tail current source coupled to the sources and bulk electrodes of the third and fourth input transistors and to the bulk electrodes of the first and second input transistors. The gates of the third and fourth input transistors are coupled to the first and second input voltage signals, respectively, and the gates of the first and second cascode transistors are coupled to the second and first input voltage signals, respectively.

Abstract: In a digital radio system including a transmitter unit and at least one receiver unit, changes to the system can implemented without modifying the hardware components by providing the transmitter unit and the receiver unit with processing capability. With respect to the transmitter unit, the principal function of the processing capability is to modify the encoding of the transmitted signal stream. The processing capability of the receiver unit provides the ability to identify when the decoding algorithms are not compatible with the transmitted signal stream. The decoding algorithms of receiver unit can be updated to be compatible with transmitted signals in several different embodiments. According to one embodiment, the updated decoding algorithm can be transmitted to the receiver unit along with, or in place of, the program signal stream. The programmable processor of the receiver unit identifies the decoder algorithm signal stream and installs the decoder algorithm in the programmable processor.

Abstract: A class AD audio amplifier system (10) with reduced noise capability in muting and unmuting events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52?) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. When the system is muted, a common mode voltage (CM_RAMP) is applied to the inputs of the comparators (39A, 39B; 52+ 52?) to suppress the duty cycle at the amplifier output, preferably to a zero duty cycle. In the transition from a muted state to an unmuted state, the common mode voltage (CM_RAMP) is ramped from the suppressing voltage to zero common mode voltage, permitting the duty cycle of the complementary PWM signals to gradually increase, thus reducing clicks and pops.

Abstract: An operational amplifier having a wide input common mode voltage range includes first (2) and second (3) differential input transistor pairs coupled to first (14) and second (15) tail current transistors. At least one of the first and second tail current transistor pairs is controlled by a common mode control circuit (4). A gate of the first tail current transistor (14) is coupled to the common mode control circuit (4) to turn the first tail current transistor on and to turn the second tail current transistor off when the common mode input voltage is below a common mode threshold voltage (CMTHR). A folded cascode stage (5) is driven by the first and second differential input transistor pairs.

Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a photoresist layer on a surface of a wafer. The wafer includes an array of die that includes a plurality of complete die and at least one partial edge die. The wafer has an edge that has a substantially rounded profile causing undersized patterns in semiconductor devices formed on partial edge die. A first exposure intensity is assigned to a first group of die on the surface of the wafer. The first group of die includes a group of complete die, and the first exposure intensity is assigned based at least in part on the location of the first group of die on the surface of the wafer. A second exposure intensity is assigned to a second group of die on the surface of the wafer. The second group of die includes at least one partial edge die. The second exposure intensity less than the first exposure intensity to compensate for reduced line width due to the wafer edge topography.

Abstract: Systems and methods are included for providing anti-aliasing in a sample-and-hold circuit. One embodiment of the present invention includes a method for sampling of an input signal for providing to an analog-to-digital converter. The method comprises generating a sample signal having a given frequency and a period that defines both a sample phase and a hold phase. The method also comprises sampling the input signal at both the sample phase and the hold phase. The method further comprises generating a decimated output sample that is an aggregate of consecutive samples of the input signal obtained during the sample phase and the hold phase.

Abstract: A fly height controller circuit for a disk drive head having a resistive heater is disclosed. The fly height controller includes an error amplifier that controls a variable current source driving the resistive heater. The error amplifier compares a desired heater power signal with a feedback power signal that is generated by a multiplier. The multiplier receives a signal corresponding to the resistive heater current, for example as generated by a second variable current source also controlled by the error amplifier, and a signal corresponding to a voltage across the resistive heater. A first differential amplifier develops a differential voltage corresponding to the heater voltage. A second differential amplifier is biased by the resistive heater current signal, and receives the differential voltage form the first differential amplifier. A differential current generated by the second differential amplifier produces the feedback power signal as an output voltage.