Abstract: Disclosed are reset techniques for a spatial light modulator, and related system for displaying an image. The systems and methods have pixels that are loaded with data and reset commands to take on binary states, where the methods employ adaptable algorithms to provide flexibility in placement of the reset commands. Specifically, valid regions for such reset commands are determined, and times for consecutive bit segments are calculated; and DMD load times are adjusted for a proper sequence. An advantage of the disclosed methods is that two consecutive bit segments are no longer restricted to following a pattern of normal/short bit segments. In contrast, with the disclosed technique short segments may be consecutive, allowing the implementation of additional enhancements, including neutral density filtering (NDF) techniques that typically include adjacent short bits in the bit sequence.

Abstract: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.

Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).

Abstract: An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.

Abstract: Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

Abstract: In a dual-channel HD radio receiver, when the broadband filter channel is compromised, the broadband channel is inactivated and the narrowband channel is activated. By mixing the signals of the two channels during the change, undesirable audio artifacts can be minimized.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.

Abstract: In a test and debug environment using a JTAG protocol to test a target processing unit, apparatus for multi-value polling permits a poll unit, associated with the scan controller, to determine whether one of several possible signal groups is present in the received data stream. The test and debug unit generates a series of numbers, each number corresponding to a preselected signal groups. The corresponding field in the received data stream is decoded to provide a series of output signals, each output signal corresponding to one group. The output signals of the decoder are compared to corresponding numbers of the expected value. When a signal from the decoder unit is found to correspond to one of the selected data number, the poll operation is a success.

Abstract: One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell and a second memory cell that share a common drain that is associated with the memory cell pair. The memory cell also includes a bitline configured to provide data from the first and second memory cells, wherein the bitline is electrically isolated from the common drain. Other methods and systems are also disclosed.

Abstract: A system for testing a lighting diode includes one or more nozzles, a probe, and a detector, where the lighting diode is operable to emit light in response to a current. The one or more nozzles direct a cooling fluid towards the lighting diode. The probe applies a current to the lighting diode. The detector detects the light emitted by the lighting diode in response to the current.

Abstract: A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.

Abstract: A piezoelectric resonator with an acoustic Bragg reflector that includes alternating layers of high and low acoustic impedance materials. The high and low acoustic impedance dielectric materials make up electrically insulating layers.

Abstract: A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is employed to implant a dopant into the target deep well region to form a deep well region with the selected region having a lowered dopant concentration. The lowered dopant concentration can yield a higher breakdown voltage for the bipolar device. The intrinsic dilute mask mitigates implantation within the selected region.

Abstract: For a given sentence grammar, speech recognizers are often required to decode M sets of HMMs each of which models a specific acoustic environment. In order to match input acoustic observations to each of the environments, typically recognition search methods require a network of M sub-networks. A new speech recognition search method is described here, which needs a network that is only the size of a single sub-network and yet provides the same recognition performance, thus reducing the memory requirements for network storage by (M-1)/M.

Abstract: Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line.

Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region.

Abstract: To protect the structural layers from being eroded in the etching process, a protection layer is deposited on the exposed structural layers of the micromirror. The protection layer is deposited before etching and removed after etching.

Abstract: Organic surfactants are employed to passivate the surfaces of MEMS devices, such as digital micromirrors. The binding of these surfactants to the surface is improved by first associating with the surface transition metal atoms or ions from Groups IVB, VB, and IVB of the periodic table.

Abstract: A projection system is disclosed herein. The projection system employs a spatial light modulator comprising an array of individually addressable pixels for modulating the incident light based on image data. The modulated light is projected on a screen for viewing.

Abstract: System and method for processing image data containing motion for display on a display device. A preferred embodiment comprises applying a filter to an input image, determining a presence of motion in the input image, and generating an output image from the input image and the filtered image based upon motion in the input image. The detection of motion in the input image permits the use of filtered image data in portions of the image containing motion, thereby taking advantage of aliasing reduction provided by the filter while allowing the use of unfiltered image data in portions not containing motion. This helps to preserve image quality since filtering softens the image.