Abstract: A buck/boost regulator controller is provided. The buck-boost regulator controller controls four switches in an H-bridge configuration to control voltage regulation. The buck/boost regulator controller includes a digital error amplifier and buck-boost control logic. The digital error amplifier provides a multi-bit digital error voltage signal that is based on the difference between the output voltage and the desired output voltage. The buck-boost control logic controls the opening and closing of the four switches in the H-bridge based, in part, on the multi-bit digital error voltage signal.

Abstract: In a snapback NMOS ESD protection structure, the output voltage presented to an internal circuit for ESD protection is limited by providing for a separate output terminal at a lower voltage than the input terminal. The voltage drop between the two terminals is achieved by connecting the input and output terminals to different parts of a ballast region of the structure and using the saturation resistance of the portion of the ballast region between the terminals to achieve the voltage drop.

Abstract: A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads.

Abstract: An improved method for manufacturing bipolar transistors is disclosed. The method for forming a PNP transistor comprises the steps of forming a P type collector on a substrate, forming a PNP epitaxial base on the P type collector, forming a PNP extrinsic base in the PNP epitaxial base, and forming a PNP emitter in contact with the PNP extrinsic base. The method for forming an NPN transistor comprises the steps of forming an N type collector on a substrate, forming a NPN epitaxial base on the N type collector, forming an NPN extrinsic base in the NPN epitaxial base, and forming an NPN emitter in contact with the NPN extrinsic base. The PNP and NPN transistors may be manufactured in the same control flow process.

Abstract: A system and method is described for providing a continuous bath wetdeck process for use in the manufacture of semiconductor wafers. The invention provides a method for extending an effective working life of a chemical bath of the type that comprises a chemical bath liquid within a chemical bath container. An amount of fresh chemical is continuously added to the chemical bath liquid and an amount of chemical bath liquid is simultaneously purged from the chemical bath container. A balance is maintained between the amount of fresh chemical that is added to the chemical bath liquid and the amount of chemical bath liquid that is purged in order to maintain the effectiveness of the chemical bath liquid to clean semiconductor wafers within the chemical bath.

Abstract: A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.

Abstract: Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay required for generating sense amplifier enable (SE) signal in a memory. The tracking circuit receives an array supply voltage (VDDAR) and a periphery supply voltage (VDDPR). Further, the circuit includes a discharge control circuit, operatively coupled to the tracking circuit, for increasing delay in activating a first transistor of the tracking circuit when VDDAR is higher than VDDPR; and a contention circuit including an output coupled to the first transistor, for delaying a discharge path activation through the first transistor when VDDAR is lower than the VDDPR.

Abstract: A circuit for recovering charge at the gate of an output transistor arranged to drive the output of a switching circuit such as a switching regulator or controller. A substantial portion of the charge for each switching cycle is recovered under a wide range of load conditions for the switching circuit, e.g., no load, partial load, or full load. Also, charge recovery operates effectively with a switching circuit that is arranged to switch in a synchronous or asynchronous manner. Additionally, if the output voltage of a switching circuit is 12 or more volts, the amount of charge that can be saved can be relatively substantial.

Abstract: Methods and systems are described for enabling the efficient fabrication of wedge-bonding of integrated circuit systems and electronic systems.

Abstract: An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract: A gate dielectric layer (500, 566, or 700) of an insulated-gate field-effect transistor (110, 114, or 122) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (502, 568, or 702) from significantly penetrating through the gate dielectric layer into the underlying channel zone (484, 554, or 684) while simultaneously avoiding the movement of nitrogen from the gate dielectric layer into the underlying semiconductor body. Damage which could otherwise result from undesired boron in the channel zone and from undesired nitrogen in the semiconductor body is substantially avoided.

Abstract: An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space.

Abstract: A wireless circuit (1100, 1190) for tracking an incoming signal and for use in a network (2000) having handover from one part (Cell A) of the network to another part (Cell B).

Abstract: A device (200, 2200) for improved security includes a processor (200) and a secure writeable memory (2245) coupled to said processor (200) and including code (2240) to download a loadable security kernel to the processor (200), authenticate the loadable security kernel, and transfer the kernel so that the kernel begins at a predetermined address inside the secure writeable memory (2245) only if the authentication is successful. A process (2400) of manufacturing a target communication device (2310) having a memory space having a secure writable portion (2245) of the memory space, the manufacturing process (2400) using a host machine (2330). The manufacturing process (2400) includes downloading (2540) the loadable security kernel from the host machine (2330) to the memory space at the target (2310). The loadable security kernel has a flashing entry point.

Abstract: A resistor-programmable device generates pulses counted by a counter. The counter's output controls a drive signal generator, such as an adjustable current source. The drive signal generator generates a drive signal (such as a current), which leads to the creation of a sense signal (such as a voltage) using a resistance. The resistance can have one of a set of specified values or fall within one of a set of specified windows. The resistor-programmable device can convert the resistance value into a digital value, which can be used to set a sensor trip point threshold or some other parameter. The digital or parameter value is independent of changes in the resistance that are within a specified tolerance. For instance, the same parameter value could be selected even when the resistance varies within some tolerance (such as 1%) as the resistor-programmable device can determine the window in which the resistance falls.

Abstract: A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

Abstract: In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.

Abstract: An apparatus and method for performing response time compensation. The apparatus described includes a first response time compensation (RTC) module for providing boosted gray level values when transitioning only from a previous gray level of zero to a first current gray level for a color of a pixel of a display. The apparatus also includes a second RTC module for providing boosted gray level values when transitioning from a previous gray level greater than zero to a current gray level for the color of the pixel.

Abstract: A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.

Abstract: In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N? type or P? type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N? and P? channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET).