Abstract: Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For each data block, there is produced a sequence of syndromes that respectively correspond to the sets of parallel data within the data block. The final syndrome in the sequence of syndromes corresponds to all of the data in the data block. The time required for CRC processing can be reduced by concurrently producing first and second ones of the syndromes that respectively correspond to first and second ones of the sets that are respectively contained in first and second ones of the data blocks.

Abstract: An electronic device (1640) includes a non-volatile store (1620) holding a plurality of encrypted sub-applications (SubApp n), and application-specific identifications (ASIDs) to respectively identify the encrypted sub-applications (SubApp n), and at least one wrapper having a representation of code to call (2220) a function (KPPA2) and supply a said application-specific identification (ASID) to the called function (KPPA2) to determine a storage location (UU) and access (2250) the storage location (UU) for contents and to call (2260) for decryption of the encrypted sub-application (SubApp n) using the contents of the storage location (UU) as a key; and a processor (1660) coupled to said non-volatile store (1620) and operable to access the representation of code and execute the code (2220, 2260). Various electronic devices, information products, processes of manufacture, and apparatus are disclosed and claimed.

Abstract: A method of sequencing wafer processing order to minimize sequence correlation in a cyclical two pattern model by generating a set of sequences of wafer identifiers that each specify an order by which one or more fabrication equipments processes wafers of a wafer lot, where the wafer lot contains a number of slots and the fabrication equipments each includes a first subsystem for processing wafers in odd-numbered slots of the first wafer lot and a second subsystem for processing wafers in even-numbered slots of the first wafer lot, and where each of the generated wafer sequences contains exactly a number of wafer identifiers that match the wafer identifiers in every other wafer sequence indexed in the set.

Abstract: A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is formed on at least the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and backside semiconductor surface. The high-k dielectric material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed while protecting the high-k dielectric layer on the topside semiconductor surface. The selective removing includes a first oxidizing treatment, and a fluoride including wet etch follows the first oxidizing treatment. The fabrication of the IC is completed including forming at least one metal gate layer on the high-k gate dielectric layer after the selectively removing step.

Abstract: An electronic circuit 120 includes a more-secure processor (600) having hardware based security (138) for storing data. A less-secure processor (200) eventually utilizes the data. By a data transfer request-response arrangement (2010, 2050, 2070, 2090) between the more-secure processor (600) and the less-secure processor (200), the more-secure processor (600) confers greater security of the data on the less-secure processor (200). A manufacturing process makes a handheld device (110) having a storage space (222), a less-secure processor (200) for executing modem software and a more-secure processor (600) having a protected application (2090) and a secure storage (2210).

Abstract: An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage node set, a second storage node set, and a set of other nodes, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type and are not connected together, where each node in the first storage node set is connected to a port in the first port set, where each node in the second storage node set is connected to a port in the second port set, where each of the other nodes is connected to one of the other ports, and where each of the other ports is connected to one and only one of

Abstract: An electronic interrupt circuit includes an interrupt-related input line, a security-related status input line, a context-related status input line, and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.

Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface.

Abstract: A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type.

Abstract: A system (100) for characterizing surfaces can include a nanotip microscope (104) in a first pressure envelope (102) at a first pressure with an electrically conductive nanotip (110) mounted thereon for characterizing a sample surface. The system can also include an ion imaging system (122, 124, 128) within a second pressure envelope (120) at a second pressure. The second pressure can less than or equal to the first pressure and the pressure envelopes (102, 120) can be separated by a pressure limiting aperture (PLA) (132). The system can further include gas sources (116, 118) for introducing into the first pressure envelope (102) at least one gas, and a voltage supply (114) coupled to the nanotip (110) for generating an electric field between the nanotip (114) and the PLA (132).

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

Abstract: A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar outer surface, and this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution such that an area portion of the active chip surface is available for attaching a thermally conductive plate; this plate has a thickness compatible with the thickness of the conductive pad layer.

Abstract: In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical source lines.

Abstract: A method of conditioning a CMP polishing pad to attain a desired thickness profile in a polished layer on a wafer is disclosed. The incoming thickness profile of the layer to be polished, the thickness profile of the polishing pad, a polish rate of layer as a function of pressure and the removal rate of polishing pad material by a conditioning block are used to compute a sweep pattern for the conditioning block which will produce a desired thickness profile on the polishing pad. The method may be applied to maintaining the desired profile on the polishing pad during the course of polishing multiple wafers. The pad profile may be adjusted to keep pressure between the pad and the wafer to a safe limit to reduce polishing defects.

Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads.

Abstract: A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.

Abstract: A silicon rich anti-reflective coating (30) is formed on a layer (10) in which narrow linewidth features are to be formed. Prior to the formation of a photoresist layer (50), the anti-reflecting coating (30) is exposed to excited oxygen species to reduce photoresist poisoning.

Abstract: System and method for adaptively allocating channels to subchannels and maintain balance on the subchannels. A preferred embodiment comprises an assignment unit (for example, assignment algorithm unit 717) that receives call/connection requests from a call/connection processing unit (for example, call/connection processing unit 712). The assignment unit may use a lookup table or channel metrics to determine an allocation for the call/connection to maintain a balance across the subchannels. The assignment unit may allocate only the call/connection in the request or it may allocate the call/connection in the request plus the calls/connections that are already allocated to achieve balance.

Abstract: An electronic circuit (1100) including a processor circuit (1110) and a storage circuit establishing a speech coder (1170) for execution by said processor (1110), the speech coder (1170) for approximating speech by pulses having pulse positions selectable from a codebook (550), the speech coder (1170) operable to obtain (1310) a set of estimated pulse positions having a first number of pulse tracks of the estimated pulse positions, use (1320) a cost function (epsilon tilde {tilde over (?)}) relating to approximation to speech to find a first subset including a second number of one or more pulse tracks fewer in number than the first number wherein the first subset of pulse tracks contributed a lower contribution to the cost function relative to a second subset of pulse tracks, and control (1330) a subsequent pulse position search beginning with the lower-contributing subset of pulse tracks to yield pulse positions to provide a value of the cost function representing a better approximation to speech.