Abstract: Cyclic redundancy check processing is applied advantageously to a set of input data that includes an unknown data portion and a data portion that is already known before the unknown data portion becomes available. A syndrome contribution that the already-known data portion contributes to a syndrome for the set of input data is determined before the unknown data portion becomes available. When the unknown data portion becomes available, the syndrome for the set of input data is determined based on the unknown data portion and the syndrome contribution.

Abstract: A local oscillator (LO) generator architecture using a wide tuning range oscillator is disclosed. In one embodiment, a wide tuning oscillator based LO generator system includes a wide tuning range oscillator for generating a signal with a first initial frequency or a second initial frequency in response to a control voltage, a first frequency controlling circuit for converting the first initial frequency of the signal into a final frequency, and a second frequency controlling circuit for converting the second initial frequency of the signal into the final frequency.

Abstract: A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.

Abstract: Method and system for false lock free autonomous scan in a receiver is disclosed. The method includes identifying a presence of a desired signal to avoid false frequency lock in a Frequency Modulation receiver. The method includes receiving a signal. The method further includes identifying the desired signal, if a first energy is above a first threshold. The method also includes identifying the desired signal, if an Intermediate Frequency count is below a second threshold. The method includes identifying the desired signal, if a second energy of the signal is above a third threshold. The method includes identifying the desired signal, if an absolute difference between a first Received Signal Strength Indication (RSSI) value and a second RSSI value of the signal is below a fourth threshold. The method includes determining a third energy. The method includes identifying the desired signal, if the third energy is below a fifth threshold.

Abstract: An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). The processor (130) is coupled to the on-chip boot ROM (132) and to the non-volatile security identification element (140) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element(140). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

Abstract: A method for film reconstruction includes identifying motion tear artifacts within a plurality of video fields of a stream of video fields. The motion tear artifacts identified by analyzing the video fields using fuzzy logic. The method also includes comparing the analysis of one video field to the analysis of an immediately preceding video field to determine whether there is a relatively high level of motion tear artifacts within the video field or a relatively low level of motion tear artifacts within the video field. The method further includes identifying a pattern of temporal periodicity for the comparisons. The method also includes determining the cadence of the stream of video fields based on the pattern of temporal periodicity.

Abstract: A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034).

Abstract: A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.

Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.

Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.

Abstract: A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement module for measuring absolute output voltages of the LDO regulators including a resistor scaling array for generating candidate voltages based on a first output voltage of the LDO regulators, a multiplexer for forwarding one of the candidate voltages selected by a binary search algorithm, and a comparator for generating a first test output by comparing the candidate voltage with an external reference voltage, and a DC load regulation measurement module for measuring corresponding DC regulation voltages of the LDO regulators including a switch for applying an internal test load to a second output voltage of the LDO regulators, and the comparator for generating a second test output by comparing a reference voltage with the second output voltage modified by the internal test load.

Abstract: An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.

Abstract: An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a first input terminal; a second pair of transistors (the second pair) that defines a second output, each transistor of the second pair having a gate coupled to a second input terminal; a first capacitor coupled to the second output terminal and to the gate of a first transistor of the first pair; a second capacitor coupled to the second output terminal and to the gate of a second transistor of the first pair; a third capacitor coupled to the first output terminal and to the gate of a third transistor of the second pair; and a fourth capacitor coupled to the first output terminal and to the gate of a fourth transistor of the second pair.

Abstract: Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime array for storing a plurality of signal values for each time instance in a predetermined time period, and a checkpoint cache for selectively storing the plurality of signal values stored in the runtime array at selected time instances. A hyper-checkpoint array is further provided to checkpoint the signal values in the checkpoint cache. In addition, the time instances and values of memory writes are also checkpointed. A user may retrieve the value of any signal values generated during the simulation run and may additionally rewind the simulator to a user-specified time in the simulation run.

Abstract: In at least some disclosed embodiments, a wireless electronic system includes a decoder module coupled to a processor. The decoder module is configured to send a signal to the processor based on a less than completely acquired burst of data. The less than completely acquired burst of data is part of a complete burst of data, and the complete burst of data is contiguous. The processor causes a reduction in power consumption of the wireless electronic system based on the signal.

Abstract: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide LC tank circuits having an inductance and a capacitance. In addition, the circuits include a flicker noise reducing switch that is operable to selectively incorporate the capacitance such that an output of the circuit operates at a frequency based on a combination of the inductance and the capacitance.

Abstract: A method and apparatus for aligning a CVD showerhead, comprising engaging a showerhead stem clamp with a showerhead stem outside of a process chamber of the CVD system. An alignment fixture is provided, and a plurality of spacer discs are positioned between the showerhead suspended from a top plate of the CVD system and heated platen. Nuts supporting the showerhead to the top plate are loosened, therein permitting the showerhead to move vertically within the process chamber. The process chamber is closed and the top plate is lowered, wherein the showerhead contacts the plurality of spacer discs. The alignment fixture is engaged with the showerhead stem clamp, therein fixing a vertical position of the showerhead with respect to the top plate, and the top plate is raised. The position of the of the showerhead is then fixed with respect to the top plate via a plurality of standoffs, an adjustment bracket, a threaded rod, and a plurality of nuts.

Abstract: A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.

Abstract: The method, system, and apparatus of source statistics based intra prediction type is disclosed. In one embodiment, a method includes classifying a four-pixel square block in an edge class (e.g., may include a DC edge class, a vertical edge class, a horizontal edge class, a diagonal edge class, and/or a planar edge class) based on an edge classifier, classifying an eight-pixel square block having the four-pixel square block and other four-pixel square blocks as a homogenous class if the four-pixel square block and the other four-pixel square blocks of the eight-pixel square block belong to the edge class, assigning a direction to the edge class of the eight-pixel square block, and determining an optimal intra-prediction type through the classification such that empirical testing of all possible ones of the edge class and the direction is avoided when the homogenous class is identified.

Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.