Patents Represented by Attorney, Agent or Law Firm Wade James Brady, III
  • Method and system for improving amplifier efficiency
    Patent number: 6930548
    Abstract: One aspect of the invention is an amplifier (10), comprising an input stage amplifier (20) coupled to an output node (81). The amplifier (10) further comprises a class D output stage (50), which comprises at least two switching elements (P1, N1) and coupled to the output node (81). The amplifier (10) also comprises a control circuit (40) coupled to the output stage (50). The control circuit (40) is operable to produce a tri-state output of the output stage (50) in response to a sensed value proportional to an amount of current that flows to the output node (81).
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: August 16, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Randall J. Stephens, Teddy D. Thomas
  • Integrated circuit leadframes patterned for measuring the accurate amplitude of changing currents
    Patent number: 6922048
    Abstract: A metallic leadframe for use with a semiconductor chip intended for operation in a changing magnetic field comprises a chip mount pad having at least one slit penetrating the whole thickness of the pad and substantially traversing the area of the pad from one edge to the opposite edge. This slit is wide enough to interrupt electron flow in the pad plane, but not wide enough to significantly reduce thermal conduction in a direction normal to the pad plane, whereby the slit is operable to disrupt eddy currents induced in the pad by the changing magnetic field.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: July 26, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Kambiz Hayat-Dawoodi
  • Reconfigurable analog-to-digital converter
    Patent number: 6914549
    Abstract: Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: July 5, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Feng Chen, Ranjit Gharpurey
  • Mobile phone transceiver
    Patent number: 6912376
    Abstract: A multiple band transceiver (10) uses a fixed frequency oscillator (34) to generate a reference signal in both receive, mode and transmit mode for each frequency band. A dual-band variable oscillator (26) is used to tune signals in receive and transmit mode. The use of the fixed frequency oscillator in both modes and in each band reduces the number of oscillating components, simplifying the circuit and reducing power requirements.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: June 28, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Donald E. Smith, Steven Lazar
  • Method and system of wire bonding using interposer pads
    Patent number: 6908843
    Abstract: The present invention discloses a method and system of wire bonding a semiconductor die to a lead using interposer pads. The use of disclosed embodiment of the present invention permits combined bonding wire lengths of up to 8 mm while reducing wire sweep, wire spacing violations and wire shorts.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: June 21, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Herald M. Baldonado, Celine R. Mandapat, Paul G. Perez
  • On-chip capacitor
    Patent number: 6897505
    Abstract: An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the interconnect structure are connected above and below to one another by metal vias to form a wall of metal which increases total capacitance by taking advantage of the via sidewall capacitance.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: May 24, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas J. Aton
  • Method of forming metal oxide gate structures and capacitor electrodes
    Patent number: 6897105
    Abstract: An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method comprising: providing the second structure; forming the electrically conductive structure of a material (step 118 of FIG. 1) that remains substantially conductive after it is oxidized; forming an electrically insulative layer (step 116 of FIG. 1) between the second structure and the conductive structure; and oxidizing the conductive structure by subjecting it to an ozone containing atmosphere for a duration of time and at a first temperature.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: May 24, 2005
    Assignee: Texas Instrument Incorporated
    Inventors: Glen D. Wilk, Robert M. Wallace, John M. Anthony, Paul McIntyre
  • Apparatus and method for automatically detecting defects on silicon dies on silicon wafers
    Patent number: 6895109
    Abstract: An apparatus and method for automatically detecting defects on silicon dies on silicon wafers comprising a silicon wafer acquisition system (30) and a computer (32) connected to said silicon wafer image acquisition system (10), wherein said computer (32) automatically aligns a silicon wafer (16), calibrates the image acquisition system (30), analyzes die images by determining a statistical die model from a plurality of dies, and compares the statistical die model to silicon die images to determine if the silicon dies have surface defects, is disclosed.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: May 17, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Floyd Schemmel, Richard Thorne
  • Semiconductor device and manufacturing method
    Patent number: 6887778
    Abstract: A semiconductor device and its manufacturing method with which the connection reliability can be improved without complicating the manufacturing process. Semiconductor chip 102 is mounted on the principal surface of insulated substrate 104, and a conductive paste containing a heat-curing epoxy resin is supplied to via holes 116 from the back of insulated substrate 104. Then, solder balls 118 are transferred onto the conductive paste of insulated substrate 104, and reflow soldering is applied in order to bond solder balls 118 to insulated substrate 104. During the reflow soldering, the heat-curing epoxy resin forms resin parts 120 around solder balls 118.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: May 3, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Masako Watanabe, Mutsumi Masumoto
  • Method for improving silicon-on-insulator (SOI) film uniformity on a semiconductor wafer
    Patent number: 6875656
    Abstract: A method for improving the thickness uniformity of a silicon-on-insulator (SOI) film on a semiconductor wafer. The preferred embodiments disclose using a selective epitaxial growth (SEG), sacrificial oxidation and an oxide removal process for improving SOI thickness uniformity. The SEG process is a leveling process that grows a materially identical layer of epitaxial silicon over the SOI layer, thus thickening the SOI layer and increasing its thickness uniformity. The sacrificial oxidation process oxidizes a portion of the newly thickened SOI layer, converting it into an oxide. An oxide removal process, commonly an etch process, removes the oxide produced by sacrificial oxidation while maintaining the thickness uniformity achieved by SEG leveling.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: April 5, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Gabriel G. Barna
  • Asymmetrical devices for short gate length performance with disposable sidewall
    Patent number: 6873008
    Abstract: An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: March 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Amitava Chatterjee
  • Method for preventing polysilicon mushrooming during selective epitaxial processing
    Patent number: 6872610
    Abstract: Methods are presented, in which an oxide protection layer is provided on a gate structure for protection against poly mushrooming during selective epitaxial silicon deposition in fabricating elevated or recessed source transistors. In one implementation, the protection layer is constructed by depositing silicon germanium over a gate polysilicon layer prior to gate patterning, and oxidizing the device to form a silicon germanium oxide over the gate polysilicon. The protection layer is then removed following selective epitaxial deposition.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: March 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Majid M. Mansoori, Zhigiang Wu
  • Method for aligning substrates in a tray
    Patent number: 6871394
    Abstract: A substrate 110 that is not lying flat on its substrate tray 100 can present significant process problems when a vacuum pickup attempts to pick up the substrate and fails due to the lack of a proper bond forming between the pickup and the substrate 110. The substrate 110 left behind on the substrate tray 100 could require human intervention. Intervention slows down the manufacturing process and increases costs. A method and apparatus to ensure that substrates are laying flat when presented to the vacuum pickup pad 220 is disclosed. A plate 320 with protrusions 320 is raised into a substrate tray 100 with holes. The protrusions 320 lift the substrates 110 up off the bottom of the substrate tray 100 and ensure that they are laying flat when presented to the vacuum pickup pad 220.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: March 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Anthony A. Barretto, Bernardo Abuan, Emory T. Mercado
  • System and method for evaluating the planarity and parallelism of an array of probe tips
    Patent number: 6870382
    Abstract: A system includes a support member and a computer system. The support member holds and retains a probe card, which has an array of probe tips extending therefrom. The computer system includes a software program. The software causes the computer system to perform a method including the following. A position where electrical contact occurs between at least some of the probe tips of the probe tip array and a selected surface is determined through testing. Data for the positions where electrical contact occurs is recorded. The recorded data is sorted for a shortest distance where electrical contact occurred between each probe tip tested and the selected surface during the testing. The sorted data group is plotted on a three dimensional cartesian coordinate system. The system may be used for evaluating the planarity of the probe tip array and parallelism of the probe tip array relative to the selected surface.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: March 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Michael P. Harris
  • System for directed molecular interaction in surface plasmon resonance analysis
    Patent number: 6870627
    Abstract: Disclosed is apparatus and method for controlled surface plasmon resonance analysis having a surface plasmon resonance sensor (200) with a derivatized surface plasmon layer (116) in optical communication with the sensor, derivatizing the surface plasmon layer and placing an analyte detection chamber (102) in fluid communication with the derivatized surface plasmon layer. The chamber is adapted (118, 120) for the generation of a molecular interaction bias across the chamber. A conjugate is provided between an analyte and a bias responsive element, wherein the analyte is reactive with the derivatized surface plasmon layer and the bias responsive element changes the response of the analyte to the molecular interaction bias. A conjugated analyte may be introduced into the chamber, generating a molecular interaction.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: March 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Jerome L. Elkind, Anita A. Strong, Andreas Hühmer
  • Programmable bandpass analog to digital converter based on error feedback architecture
    Patent number: 6864818
    Abstract: A delta sigma modulator based analog to digital converter is presented, having a first quantizer and a digital error feedback system comprising a second quantizer and a digital bandpass noise shaping system. The second quantizer provides a second quantized output to the noise shaping system according to the first quantized output, the system analog input, and the noise shaped feedback signal. The digital noise shaping system provides a feedback signal to the first quantizer according to the second quantized output, where the feedback signal is bandpass noise shaped with respect to a quantization error of the first quantizer.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: March 8, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Rahmi Hezar
  • System for directed molecular interaction in surface plasmon resonance analysis
    Patent number: 6862398
    Abstract: Disclosed is apparatus and method for controlled surface plasmon resonance analysis having a surface plasmon resonance sensor (200) with a derivatized surface plasmon layer (116) in optical communication with the sensor, derivatizing the surface plasmon layer and placing an analyte detection chamber (102) in fluid communication with the derivatized surface plasmon layer. The chamber is adapted (118, 120) for the generation of a molecular interaction bias across the chamber. A conjugate is provided between an analyte and a bias responsive element, wherein the analyte is reactive with the derivatized surface plasmon layer and the bias responsive element changes the response of the analyte to the molecular interaction bias. A conjugated analyte may be introduced into the chamber, generating a molecular interaction.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Jerome L. Elkind, Anita A. Strong, Andreas Hühmer
  • Composite lid for land grid array (LGA) flip-chip package assembly
    Patent number: 6861292
    Abstract: A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back surface of the die with a low-modulus thermal gel, and the second material is disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferable, at least twice that of the first material.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Tz-Cheng Chiu
  • Method of fabricating a molded package for micromechanical devices
    Patent number: 6858910
    Abstract: A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by lining the cavity surfaces of the top and bottom mold halves with a protective plastic film, which also protects the surfaces of the components during the molding phase, selectively encapsulating the bonding pads and coupling members of the chip while leaving empty space above the components, and attaching a lid over the components. A molding method as well as a molding apparatus are provided compatible with the sensitivity of the micromechanical devices, yet flexible with regard to the technique used to assemble the chip and the substrate. Furthermore, the method disclosed is flexible with regard to the material and the properties of the substrate.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: February 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Anthony L. Coyle, George A. Bednarz
  • Method for data packet acquisition using split preamble
    Patent number: 6859899
    Abstract: A data packet type communication system utilizes packet framing wherein preambles are split into two or more subpreambles, separated by a number of data or a priori known symbols. A receiver chooses among individual and combined subpreamble options for determining synchronization. When a noise impulse prevents detection of one subpreamble, the impulse is detected, and preamble correlation proceeds using an unaffected subpreamble. When no impulse is detected, combined subpreambles are used.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: February 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Ofir Shalvi, Daniel Wajcer