Abstract: Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip.

Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.

Abstract: A method of laser annealing a workpiece for reduction of warpage, slip defects and breakage, the method comprising (a) moving a workpiece through a laser beam in a x-axis first direction, (b) moving the workpiece in a y-axis second direction, (c) moving the workpiece through a laser beam in a minus x-axis first direction and repeating (a)-(c) until the workpiece is fully annealed in two successive laser annealing iterations.

Abstract: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.

Abstract: One embodiment of the present invention relates to a method for which a two mask lithography process can be used to reduce design density. The two mask process uses a first mask to expose a first photoresist layer located above a hard mask layer. The first photoresist is exposed in such a way that the level forms one or more lines, on opposite sides of a cell boundary. The hard mask is then etched. A second photoresist layer is deposited above the hard mask. The second mask is used to expose the second photoresist layer in such a way that a space is formed along the cell boundary equal to the minimum space of the level as required by the design rules. The hard mask is then etched again. The hard mask is subsequently used to pattern the layer below it. Other methods and structures are also disclosed.

Abstract: Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer over at least a portion a surface of the substrate, wherein the sacrificial scattering layer includes an amorphous material. The method further includes ion implanting a dopant through the sacrificial scattering layer to within a depth profile in the substrate. Subsequently, the sacrificial scattering layer can be removed such that erosion of the substrate surface is less than one percent of a thickness of the sacrificial scattering layer.

Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract: A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.

Abstract: Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.

Abstract: In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can comprise forming a first layer over a semiconductor substrate, forming a first mask layer over the semiconductor substrate, and using the first mask layer to pattern first features. The method can also include forming a second mask layer over the first features, using the second mask layer to pattern portions of the first features, removing the second mask layer, and removing the first mask layer.

Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

Abstract: The present disclosure is directed a method for preparing a system of photomask patterns for implementing a drawn pattern on a substrate with a multi-patterning lithography process. The method comprises receiving data describing a drawn pattern. A first photomask pattern is formed for implementing a region of the drawn pattern on the substrate. A second photomask pattern is formed comprising one or more pattern features having longitudinal edges for implementing the region of the drawn pattern on the substrate, wherein at least 90% of all the longitudinal edges of the second photomask pattern that are positioned within the region are oriented in substantially the same direction. Both a system for forming the photomask patterns and a process for patterning a device using the photomask patterns are also disclosed.

Abstract: The present disclosure is directed to a method for preparing photomask patterns for a lithography process that employs a plurality of photomasks. The method comprises receiving data describing a drawn pattern. An edge of the drawn pattern is identified that can be defined using a first photomask and a second photomask, and the first photomask is chosen for patterning the edge. Patterns are formed for the first photomask and the second photomask, wherein the first photomask pattern is formed to pattern the edge, and the second photomask pattern is formed to have a wing adjacent to the edge for protecting the edge from double patterning. A process for patterning an integrated circuit device is also disclosed.

Abstract: Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.

Abstract: In accordance with the invention, there is provided a system and method for checking a mask layout including sub-resolution assist features (SRAFs). A checking program divides each edge of each main feature into sections, forms a set of segments by searching perpendicularly over a distance to determine if any portion of a feature is located within the distance. Segments are then flagged based on whether a feature located within proximity to that segment. A classification program may then classify each of the main features based on the segment data.

Abstract: An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.

Abstract: Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is currently no production floor capability for mapping chemical contaminants across an electronic device substrate on a routine basis. A scanning surface chemical analyzer for mapping the distributions of a variety of chemicals on substrates is disclosed. The analyzer includes an array of sensors, each of which detects a single chemical or narrow range of chemicals, a scanning mechanism to provide a mapping capability, an electrical signal analyzer to collect and analyze signals from the array of sensors and generate reports of chemical distributions, and an optical desorption mechanism to amplify detection. A preferred embodiment includes an array of miniature quadrupole mass spectrometers in the sensor array. Scanning modes include whole substrate mapping, region sampling, and spot sampling of known defect sites.

Abstract: An embodiment relates generally to a method of testing a mixed signal device. The method includes monitoring multiple parameters of the mixed signal device and scanning the mixed signal device with an optical source. The method also includes forming multiple windows, where each window is assigned to a respective parameter. The method further includes comparing an image from a respective image to a reference image to determine an existence of an anomaly.

Abstract: The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.

Abstract: A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed on the substrate. The NMOS fin includes a channel on the substrate at one of 0° and 90° to the PMOS fin and includes a second surface of a second crystal orientation.