Abstract: A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an anneal and an exposure to hydrochloric acid. The anneal and acid exposure can be performed within an epitaxial reactor chamber to minimize wafer transport.

Abstract: A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.

Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.

Abstract: A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.

Abstract: In accordance with the invention, there is a method of designing a lithography mask. The method can comprise generating initial phase photomask data and initial trim photomask data from a first set of data from a first drawn layer and/or layout and a second set of data from a second drawn layer, combining the initial phase photomask data with the first set of data to form a combined layer, inspecting for gaps in the combined layer, and processing the gaps in the combined layer.

Abstract: A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness<the second thickness. A substrate having a semiconducting surface is provided. A pad dielectric layer having a thickness?the second thickness is formed on the semiconductor surface including over the second regions, wherein the pad dielectric layer provides at least a portion of the second thickness for the second gate dielectric. A hard mask layer is formed on the semiconductor surface including over the second regions. A plurality of trench isolation regions are formed by etching through the pad dielectric layer and a portion of the semiconductor surface.

Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.

Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

Abstract: A system and method which stores a three dimensional physical representation of an electrical circuit such as an integrated circuit design uses a database having a plurality of files to store active trace data and inactive feature data (layout data). The data from each file can be cross mapped with schematic data. A netlist or some other correlation method can be used to correlate the data from each of the individual files such that the leads of the layout data are correlated to leads from a schematic to maintain compatibility between the netlist and the layout data. Segmenting data into individual files decreases load times while correlating data with the netlist ensures electrical data is valid and suitable for characterization and optimization of the layout data. Various other embodiments are also described.

Abstract: A method is disclosed for forming an integrated circuit including a common gate FinFET device and a split gate FinFET device. Taller fins and shorter fins of different heights are formed in a semiconductor surface. Layers of gate dielectric material and gate electrode material are formed over tops and sides of the fins. The gate electrode material layer is planarized using chemical-mechanical polishing to remove the gate electrode material from the tops of the taller fins, leaving the gate electrode material over the tops of the shorter fins. The planarized material is patterned to form split (dual) gate structures on the sides of the taller fins and common gate structures on the tops and sides of the shorter fins.

Abstract: A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal oxidation process together with the formation of LOCOS isolation structures (3) for element seaaration of low voltage PMOS and NMOS transistors (Tr3, Tr4), and has a thinner gate dielectric layer (gate-insulation film 25 of, e.g., 7 nm) for a high voltage NMOS transistor (Tr2) that is formed simultaneously in a second thermal oxidation process together with the formation of gate dielectric layers (gate-insulation films 33, 42) of low voltage PMOS and NMOS transistors (Tr3, Tr4).

Abstract: In one aspect there is provided a gray scale lithographic mask that comprises a transparent substrate and a metallic layer located over the substrate, wherein the metallic layer has tapered edges with a graded transparency. The lithographic mask, along with etching processes may be used to transfer a pattern 450a into a layer of a semiconductor device.

Abstract: A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.

Abstract: A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures extending substantially perpendicular from an upper surface of the substrate, directing an ion beam toward the substrate, the plurality of shadowing structures interrupting an incident angle of the ion beam to define implanted and non-implanted portions of the substrate. The method further includes measuring the dose of implanted species within the substrate, determining an implanted surface area as a function of measuring the dose of implant, determining non-implanted surface area based on the implanted surface area, and obtaining the ion beam angle as a function of the non-implanted surface area.

Abstract: An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).

Abstract: One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.

Abstract: A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.

Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.

Abstract: Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.