Patents Represented by Attorney, Agent or Law Firm Wayne P. Bailey
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Patent number: 6154797Abstract: A plurality of transmitters are multiplexed to a hub through clocked serial links. Timing problems that may arise when switching between links are eliminated with a system including a group serial receiver for each link for performing serial to parallel conversion of data sent over the serial link, outputing a group clock signal based on the serial clock signal, outputing parallel data clocked by the group clock signal, and determining a data enable signal from the serial link. A select signal for determining the serial link being read by the hub selects the corresponding group clock, parallel data, and data enable. A load control clocks the selected parallel data into a first-in, first-out buffer using the selected group clock when the selected data enable is asserted. When the selected data enable is not asserted, the load control is held in reset and, hence, is insensitive to irregularities in the selected clock signal due to switching between links. Data is clocked from the buffer by a local clock.Type: GrantFiled: August 10, 1999Date of Patent: November 28, 2000Assignee: Storage Technology CorporationInventors: William Burns, Michael Lucas
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Patent number: 6101060Abstract: A method and associated apparatus for reduction of data loss errors in computer data tape transport applications. In tape transport devices with moveable read heads (i.e. auto-tracking read/playback heads), by sensing telemetry information regarding tape movement and alignment of a position on the tape medium before the position on the tape encounters the moveable head. Prior systems provided for such sensing only as the tape was read by the moveable head such that compensation could be made only for subsequent read operation. By sensing the telemetry data in advance of the tape encountering the moveable head, the head may be adjusted in time to encounter the misaligned tape medium compensating for the misalignment. Similarly, telemetry data relating to the speed of the tape motion as sensed by a channel reading a predetermined recorded sequence of bits permits compensation for both erroneous tape speed and tape medium stretch or contraction.Type: GrantFiled: May 28, 1999Date of Patent: August 8, 2000Assignee: Storage Technology CorporationInventors: Matthew Peter Wojciechowski, Joe Kent Jurneke
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Patent number: 6084740Abstract: The optical servo system for a tape drive that functions to align a read/write head with the data tracks written on a recording surface of a tape by reading optical servo tracks that are formed on the back side of the tape. This process decouples the magnetic recording of data on the recording surface of the tape from the optical servo system which makes use of servo tracks formed on the back side of the tape. The data storage capacity of the tape is increased since the entire recording surface of the tape is filled with data tracks and the precise alignment of the read/write head makes it possible to place the data tracks closer together. Regions of contrasting reflectivity or phase are also provided on a surface of the read/write head to enable the optical servo system to view an image of both the read/write head and the entire back side of the tape to thereby align the movable read/write head with the data tracks.Type: GrantFiled: December 1, 1997Date of Patent: July 4, 2000Assignee: Storage Technology CorporationInventors: Michael Lawrence Leonhardt, Scott David Wilson
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Patent number: 6064588Abstract: A logically complementary pair of charge storage capacitors are employed in each memory cell of an embedded dynamic random access memory (DRAM) segment. The complementary capacitors establish a data bit signal from each cell by a relative difference in charge stored on the capacitors. The adverse influences of noise are reduced or eliminated because the noise will generally equally effect both of the complementary capacitors, as well as complementary bit lines connected to the capacitors. Differential sensing of the bit line signals also avoids the influence of noise. A capacitor reference potential conductor distributes substantially equal capacitor reference voltage to each capacitor to allow each capacitor to charge and discharge more uniformly under the influence of noise.Type: GrantFiled: March 30, 1998Date of Patent: May 16, 2000Assignee: LSI Logic CorporationInventor: Harold S. Crafts
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Patent number: 6052765Abstract: The present invention provides a method for selectively storing data files on a multiple volume cartridge (MVC) device which maximizes the likelihood of gaps in stored data appearing at the end of a cartridge. All incoming data files are initially stored in a virtual disk buffer, and checked to determine time of expiration. The expiration information is then used to reorder the virtual data volume files when placed on the MVC device so that the last to expire is stored first, and the first to expire is stored last.Type: GrantFiled: April 21, 1998Date of Patent: April 18, 2000Assignee: Storage Technology CorporationInventors: Stephen H. Blendermann, Alan Ray Sutton
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Patent number: 6049798Abstract: A system resource monitor is provided to capture a data processing system's internal resource utilization, such as memory, CPU, or peripheral device availability/utilization. The captured `state` of the data processing system's resources is maintained in real-time, while the impact on the system's performance in providing such information is kept to a minimum. This is accomplished through a combination of various techniques, including specialized device drivers for the respective devices coupled with a unique data reduction technique. Such techniques include filtering only events which are of interest and combining similarly related events to reduce data processing requirements. This real-time support provides an immediate and accurate representation of the internal operations of the data processing system. Further, these resources can monitored at the process level of a multiprocessing system.Type: GrantFiled: June 14, 1994Date of Patent: April 11, 2000Assignee: International Business Machines CorporationInventors: David Addy Bishop, Timothy Manfred Holck, Telford Knox, Jr., Charles Lincoln Raby, Robert Charles Shay, Mark David Turner, Stephen Asa Yeamans
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Patent number: 6042474Abstract: A ventilation unit for operative arrangement within an electronic apparatus. This unit has: an exterior side having a first exhaust port separated from, and located in stacked relationship with, a second exhaust port; and a first and second powered air mover, each having an intake side oriented at an angle greater than zero degrees from the exterior side. The first powered air mover intake side is in communication with the first exhaust port. One powered air mover can be located closer to the exterior side than the other. Gas, such as air, removed from the electronic apparatus can be drawn in through an intake side of the second powered air mover, then directed through a duct cover before it flows between a covered side of the first powered air mover and a support member side of the unit. The angle of orientation is preferably between twenty and one-hundred degrees. Additional powered air movers can be accommodated, each with a respective exhaust port.Type: GrantFiled: June 4, 1997Date of Patent: March 28, 2000Assignee: LSI Logic CorporationInventors: Robert T. Harvey, Tina M. Reintjes
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Patent number: 6038639Abstract: The present data file storage management system for snapshot copy operations maintains a two level mapping table which enables the data files to be copied using the snapshot copy process and only having to update a single corresponding mapping table entry when the physical location of the data file is changed. The snapshot copy updates to the contents of the first level of the two level mapping table are stored on the backend data storage devices to provide a record of the snapshot copy operation which can be used to recover the correct contents of the mapping table. This record of the snapshot copy operations remains valid even though the physical location of a copied data file instance is subsequently changed. Furthermore, the physical storage space holding the updated portions of the first level of the two level mapping table can be managed using techniques like those used to manage the physical storage space holding data file instances.Type: GrantFiled: September 9, 1997Date of Patent: March 14, 2000Assignee: Storage Technology CorporationInventors: John Timothy O'Brien, Jay Stuart Belsan, Michael Steven Milillo
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Patent number: 6031676Abstract: A tape deck system uses four sensors to read features on a tape cartridge to determine control operations. A first sensor determines and a second sensor indicate a condition from a set comprising standard tape cartridge present with file protect, standard tape cartridge present without file protect, cleaning cartridge present, and a standard cartridge quiescent state. The remaining two sensors are used with a special cartridge. The special cartridge has features that indicate, to the first two sensors, that the tape deck system is in the standard cartridge quiescent state. A third and fourth sensors then read features on the special cartridge indicating cartridge type and file protect status. This system allows special cartridges, such as those that may contain thin tape, to only be accessed by tape deck systems equipped to handle the special cartridges. The sensor for indicating the special cartridge type may be modified to also indicate that the cartridge is properly seated in the tape deck.Type: GrantFiled: April 9, 1998Date of Patent: February 29, 2000Assignee: Storage Technology CorporationInventors: Leon C. Oenes, Thomas D. Steury, Philip M. Morgan
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Patent number: 6018429Abstract: A magnetic tape servo pattern including track identification. Information from a track identification area intersecting one or more tracks on each frame in combination with information identifying the track as odd or even, is used to uniquely identify the track.Type: GrantFiled: December 18, 1998Date of Patent: January 25, 2000Assignee: Storage Technology CorporationInventors: John Paul Mantey, Steven Gregory Trabert, Ronald Dean Gillingham, Richard Lewis O'Day
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Patent number: 6003109Abstract: A method and apparatus for processing interrupts for a plurality of components connected to and sharing an interrupt line in a data processing system in which interrupts are level sensitive interrupts. The components are connected to the interrupt line by interrupt connections, such as a pin. An interrupt is detected when the interrupt line is in a first state, while an interrupt is absent when the interrupt line is in a second state. Other interrupts cannot be processed while the interrupt line is in a first state. In response to detecting one or more interrupts, the connection associated with the component, for which one or more interrupts are generated, is disabled until all of the interrupts are processed. Disabling the interrupt connection allows the interrupt line to return to the first state and for additional interrupts for other components connected to the interrupt line to be detected and processed.Type: GrantFiled: August 15, 1997Date of Patent: December 14, 1999Assignee: LSI Logic CorporationInventors: Barry Elton Caldwell, Larry Leon Stephens
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Patent number: 5987085Abstract: A phase locked loop, which does not require a local reference clock to obtain a frequency lock. The circuit includes a frequency locked loop and a phase locked loop in which the frequency locked loop does not require a local reference clock. The frequency locked loop includes a transition counter having an input for data with an output connected to a charge pump. This charge pump is connected to a loop filter, which in turn is connected to a voltage controlled oscillator. The output of the voltage controlled oscillator is connected to a second input in the transition counter. The phase locked loop includes a phase detector with an input for data. The output of this phase detector is connected to a second charge pump, which has it output connected to the loop filter. The output of the voltage controlled oscillator also is connected to the input of the phase detector.Type: GrantFiled: March 26, 1997Date of Patent: November 16, 1999Assignee: LSI Logic CoporationInventor: Michael B. Anderson
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Patent number: 5983306Abstract: A bus bridge circuit having at least one register to store address ranges to enable or disable prefetch in upstream memory read transactions or upstream write transaction buffering/posting data to specific devices. The use of address ranges allows the present invention to provide selectable control of prefetch for upstream memory read transaction flow. This feature allows the continued use of read prefetch for targets that allow upstream read prefetch while disabling upstream read prefetch for targets that do not allow upstream read prefetch. Additionally, the use of the address range allows upstream memory write transaction flow without utilizing data buffering or posting for specific targets. This feature provides immediate delivery of upstream data to selected targets by selectively disabling buffering/posting of upstream memory write commands as performed by a FIFO buffer.Type: GrantFiled: September 12, 1997Date of Patent: November 9, 1999Assignee: LSI Logic CorporationInventors: Brian E. Corrigan, Alan D. Rymph
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Patent number: 5973952Abstract: A shielding conductor is spaced from a matrix of memory cells in a dynamic random access memory (DRAM) to shield the memory cells from noise signals, such as the noise created by components of a system level integrated circuit (SLIC). The shielding conductor is connected to one of a reference or potential source, preferably external to the DRAM segment. The shielding conductor distributes the effect of noise and maintains a uniform reference potential with respect to the DRAM components with which it overlays or connects. The shielding conductor comprises a plurality of connected intersecting conductors which form a mesh which overlays substantially the entire matrix. The mesh is connected to components, such as an isolating well or a capacitor reference potential conductor, at a plurality of spaced-apart locations over the entire matrix. The shielding conductor may also be a single integral conductor which overlays the entire matrix, including the bit and word lines.Type: GrantFiled: March 30, 1998Date of Patent: October 26, 1999Assignee: LSI Logic CorporationInventor: Harold S. Crafts
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Patent number: 5966599Abstract: A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.Type: GrantFiled: May 21, 1996Date of Patent: October 12, 1999Assignee: LSI Logic CorporationInventors: John D. Walker, David W. Daniel
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Patent number: 5966547Abstract: A method and apparatus for efficiently posting entries to a queue within the data processing system. Entries are posted by first processor with the entries being handled by second processor in the data processing system. The interrupt state associated with the queue is checked by the first processor. If the interrupt state is clear, then the entry is posted to the queue. This interrupt state is cleared only when all entries have been cleared from the queue by the second processor. In this manner, an efficient posting of entries to the queue may be accomplished.Type: GrantFiled: January 10, 1997Date of Patent: October 12, 1999Assignee: LSI Logic CorporationInventors: Stephen C. Hagan, Keith W. Holt
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Patent number: 5963828Abstract: A method in a semiconductor process for forming a layer of a selected compound on a substrate of a semiconductor device. A layer of titanium is formed on the substrate as a sacrificial layer. The layer of titanium is reduced using a gaseous form of a fluorine containing compound in which the fluorine containing compound includes the selected compound that is to be formed on the substrate of the semiconductor device.Type: GrantFiled: December 23, 1996Date of Patent: October 5, 1999Assignee: LSI Logic CorporationInventors: Derryl D.J. Allman, Verne C. Hornback, Ramanath Ganapathiraman, Leslie H. Allen
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Patent number: 5963422Abstract: The invention provides exemplary systems and methods for releasably securing a data storage device within a data storage system. In one exemplary embodiment, the invention comprises a cabinet which defines an enclosure. The data storage device is removably held within the enclosure. A cover is further provided which comprises a pivot end and a latch end. The pivot end is pivotally attached to the data storage device so that pivoting of the cover will release the data storage device at least partially from the enclosure. A cover latch is operably attached to the latch end, with the cover latch engaging the data storage device to prevent pivoting of the cover when the cover is closed.Type: GrantFiled: June 30, 1997Date of Patent: October 5, 1999Assignee: LSI Logic CorporationInventors: Gary L. Golobay, Robert T. Harvey
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Patent number: 5956492Abstract: A first-in-first-out (FIFO) memory system. The FIFO memory system contains a first fall-through FIFO having an input and an output. A pointer-based FIFO having an input and an output, wherein the input of the pointer-based FIFO is connected to the output of the first fall-through FIFO. The FIFO memory system also includes a second fall-through FIFO having an input and an output, wherein the input of the second fall-through FIFO is connected to the output of the pointer-based FIFO, wherein data placed into the input of the first fall-through FIFO appears at the output of the second fall-through FIFO in a first-in-first-out basis.Type: GrantFiled: March 29, 1996Date of Patent: September 21, 1999Assignee: LSI Logic CorporationInventors: Mark J. Jander, Jeffrey D. Kasyon
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Patent number: 5956723Abstract: A method for maintaining login service parameters includes a step of allocating space for and storing a login service parameter portion of a logged in port. A login service parameter of a logged in port is then compared with stored login service parameter structures. If the login service parameter of the logged in port, except for a login service parameter portion thereof, is identical with one of the stored login service parameters, a step of adding a first pointer to that stored login service parameters structure into the stored login service parameter portion structure is carried out. A new login service parameter portion structure is allocated and the process repeated, thereby creating a linked list of login service parameter portion structures, each login service parameter portion structure pointing to both the stored login service parameter structure and to a next login service parameter portion structure.Type: GrantFiled: March 21, 1997Date of Patent: September 21, 1999Assignee: LSI Logic CorporationInventor: Jieming Zhu