Abstract: A low-gain, low-jitter VCO circuit implemented in CMOS provides center frequency adjustment to overcome process variations. Further, noise immunity is improved by using a separate feedback loop to provide the nominal current biasing for the oscillator chain. This feedback loop coarsely sets the center frequency. The actual control of the oscillation frequency is achieved by a second current source, whose output is added to the nominal bias current to provide a total bias to the oscillator. This second current source "fine tunes" the oscillator frequency responsive to a control signal. Because two separate current sources are used, the circuit can realize a high oscillation frequency with a low VCO gain. Another feature provides for adjusting the center frequency in response to a digital input word provided via external pins, or from internal logic or memory. The center frequency thus can be calibrated by measurement at the time of manufacture, or changes later by the end user or by other circuitry.

Abstract: A phase-locked loop circuit including a divider unit that receives a serial data stream at its input and generates a parallel data stream. The parallel data stream has a slower clock rate than the serial data stream according to the present invention. A phase detector unit has an input connected to the output of the divider unit for receiving the parallel data stream generated by the divider unit. The phase-locked loop circuit further includes a voltage controlled oscillator having an input connected to the output of the phase detector unit. The output of the voltage controlled oscillator is connected to another input of the phase detector, wherein the phase detector unit generates error signals that are sent to the voltage controlled oscillator.

Abstract: A method for dynamic reconfiguration of a message-passing interface from a Push model to a Pull model is disclosed. In the Push model, a host computer device moves data stored in a host local memory to an I/O peripheral shared memory, whereas in the Pull model, the I/O peripheral moves data from the host's shared memory to a local memory of the I/O peripheral. To dynamically reconfigure the message passing interface from the Push to the Pull model, the hosts waits for the I/O peripheral to cycle through power-on/reset, locates the I/O peripheral's inbound and outbound queues in memory, directs the I/O peripheral to clear its outbound queue of messages from previous inbound messages and initializes the allocated message frames as free messages. The host then posts a message to the I/O peripheral inbound queue instructing the I/O peripheral to initialize in the Pull model. The I/O peripheral then posts any messages currently being processed to the I/O peripheral outbound queue.

Abstract: A redundant storage control module (also referred to as RDAC or multi-active controller) maintains a queue of pending I/O requests sent for processing via a first asynchronously operating I/O path. In the event of failure of the first asynchronously operating I/O path, the controller restarts the entire queue of pending I/O requests to a second I/O path without waiting for each request to individually fail from the first path. Some prior techniques required the RDAC module to await failure of each I/O request sent to the failed first I/O path before restarting each failed request on the secondary I/O path. Such techniques greatly extend the total time required to restart all operations sent to a failed I/O path, by awaiting the failure of all I/O requests previously sent to the first I/O path.

Abstract: A data processing system that includes an improved architecture for providing hot spare storage devices. Specifically, the data processing includes a bus that is connected to one or more computer systems and a number of storage subsystems. Each storage subsystem includes storage devices and a controller. The controller in a storage subsystem provides the connection to the bus and an interface for controlling data transfers to and from the storage device. A backup storage system is connected to the bus. The data processing system also includes a detection means for detecting a failure of a storage device within one of the plurality of storage subsystems and a backup means for using the backup storage device to replace the failed storage device.

Abstract: A method and apparatus for controlling access to a bus. A target having a period of unavailability is identified. A master device requesting access to the bus to initiate a data transfer between the master device and the target device also is identified. The master device is denied access to the bus for a delay period in response to the master device attempting to retry a data transfer with the target device, wherein the delay period is a time period after which the target device becomes available for additional transfers, wherein the bus is available to other master devices during the delay period.

Abstract: A RAID storage system which attempts to balance the I/O workload between multiple redundant array controllers is presented. The RAID storage system of the invention utilizes a plurality of redundant array controllers which require static ownership of storage devices for WRITE access requests to the same redundancy parity group. Accordingly, a plurality of storage devices are provided in the system, each of which is owned by one of the redundant array controllers. Each storage device is coupled to both its owner controller and at least one other array controller. Each array controller coupled to a storage device has the ability to read and write data from and to the storage device. Each array controller has a processing queue from which pending read and write access requests are removed and then processed one at a time by the controller. A host computer is provided for dispatching read and write access requests to the redundant array controllers.

Abstract: A cache memory control architecture within a RAID storage subsystem which simplifies the migration and porting of existing ("legacy") control methods and structures to newer high performance cache memory designs. A centralized high speed cache memory is controlled by a main memory controller circuit. One or more bus bridge circuits adapt the signals from the bus architecture used by the legacy systems to the high speed cache memory. The bus bridge circuits each adapt, for example, a PCI bus used for a particular cache access purpose to the signal standards of an intermediate shared memory bus. The main memory controller circuit adapts the signals applied to the intermediate shared memory bus to the high speed cache memory bus. The hierarchical bus architecture permits older "legacy" control methods and structures to be easily adapted to newer cache memory architectures.

Abstract: Methods and associated apparatus for coordinating file lock requests from a cluster of attached host computer systems within I/O controllers (e.g., intelligent I/O adapters) attached to a storage subsystem. The I/O controllers, operable in accordance with the methods of the present invention, includes semaphore tables used to provide temporary exclusive access to an identified portion of an identified file. The host systems request the temporary exclusive access of a file through the I/O controllers rather than over slower network communication media and protocols as is known in the art. The I/O controllers then manages a plurality of competing lock requests to provide mutual exclusivity of the file access. The file lock management is therefore managed over the higher bandwidth storage interface channels of the host systems and without the generalized network protocols burdening the lock management process and the host system CPUs.

Abstract: In a multiprocessor data processing system including at least one main processor and one sub-processor utilizing a shared queue, queue integrity is maintained by associating a semaphore with each queue entry to indicate ownership of that queue entry. Ownership of a queue entry is checked by a processor attempting to post to the queue entry. Upon determining that the queue entry is available to the processor, the queue entry is loaded by an atomic write operation, ownership of the queue entry transferred to another processor, and the other processor may be alerted of the post to the queue. The other processor maintains ownership of the queue entry until the other processor has read and saved the data from the queue entry. Items may thus be posted to the queue and cleared from the queue by a processor independent of the state of the other processor.

Abstract: A differential current mode driver is provided with output source and sink currents that remain nearly equal in magnitude and opposite in direction throughout normal, power-down, and power-up modes of operation. Three time constants are employed to regulate these different modes of operation. The differential current mode driver includes a first time constant to stabilize the output source and sink currents during the on-state, a second time constant to control the transition from the on-state to tristate, and a third time constant to control the transition from tristate to the on-state, all the while maintaining equal source and sink currents.

Abstract: A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.

Abstract: This interconnect chip provides the function of an antifuse device. The interconnect chip is initially disconnected. Application of a high voltage applied across two terminals on the chip causes intrinsic polysilicon, which serves as an insulator between the connections to break down and form a reliable short circuit between the pads by redistribution of impurities from the layers above and below the intrinsic polysilicon.

Abstract: To provide high purity gases to manufacturing tools, a gas isolation box is employed which is formed of stainless steel and includes vertical slots for receiving gas stick carrier cards. Gas sticks include required valves, gauges, and regulators rigidly mounted on stainless steel carrier cards, leak tested and labeled. The carrier cards with the rigidly mounted, leak tested gas sticks are slid into the vertical slots of the gas isolation box. Only two connections are then required to complete to gas lines, reducing the potential for flexing of high purity gas lines during installation.

Abstract: A method for transferring data from a first device to a second device where the second device has a main data processor and a secondary processor associated therewith. The method includes the steps of (1) transferring a data stream having a control portion and a data portion from the first device to the second device, and (2) processing the data portion with the secondary processor in accordance with the control portion without interrupting the main data processor. A multi-controller apparatus which is useful for practicing the method is also disclosed.

Abstract: A method of setting a plurality of addresses is disclosed. The method includes the step of setting a first module identifier for a first device module. The method further includes the step of setting a first address for a first device, said first address comprising an upper section and a lower section. The method also includes the step of setting a second address for a second device, said second address comprising an upper section and a lower section, wherein the step of setting the first address for the first device includes the steps of setting the upper section of the first address to the first module identifier, and setting the lower section of the first address to a first value; and wherein the step of setting the second address for the second device includes the steps of setting the upper section of the second address to a second value, and setting the lower section of the second address to the first module identifier.

Abstract: A DRAM array embedded in an IC, ASIC or a SLIC includes a plurality of redundant functional elements and a substitution circuit which responds to signals communicated from a bus to electrically connect selected ones of the redundant elements as fully functional replacements for corresponding defective elements of the DRAM array. The redundant elements include bit blocks and word line groups. The substitution circuit includes a controllable selector which electrically connects selected ones of the bit blocks and word lines to respond to data and address signals communicated on the bus. A register responds to bus control signals and supplies signals to achieve connection of the redundant elements. The defective elements are identified, and the replacement redundant elements are substituted, by testing the elements of the DRAM array for proper functionality and processing the results of the test.

Abstract: In a multifunction PCI device containing identical backend functions or other large, redundant functional blocks, a single backend function is selected as a primary function while in test mode. All backend I/O channels are then simultaneously tested in parallel, with the same data and control signals from a PCI local bus being driven to all backend channels during the same test clock cycle. A single backend channel is designated as the primary for providing requisite handshaking signals during output to the backend I/O channels. Input data from each backend channel is received in parallel and compared, with miscompares being flagged to allow testing of the input data path from the respective backend I/O channel. Only signals from the primary backend I/O channel are designated for transmission to the PCI local bus. Signals from the remaining backend channels are received in parallel with and compared to the signals from the primary channel, and miscompare flags are generated for any discrepancies identified.

Abstract: A method and apparatus for detecting when a second object touches a digitizing panel while a first object is touching the digitizing panel is disclosed.

Abstract: A reprogrammable address selector is incorporated in an embedded DRAM array which has a plurality of addressable DRAM components. The reprogrammable address selector responds to an address signal defining a unique response address. One of a plurality of selected response addresses may be electrically and selectively programmed into the selector as a substitute for a fixed response address. Thereafter the addressable DRAM component responds to the programmed response address rather than the fixed response address. The programmed response address is programmed from address signals applied on the bus.