Abstract: A method of recovering a clock signal which is embedded in an incoming data stream. The method includes the steps of providing the incoming data stream to a data sampler circuit, first operating the data sampler circuit to select one of a plurality of clock phases wherein the selected clock phase is indicative of the embedded clock signal, generating a recovered clock signal based on the selected clock phase, second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal, and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode. An apparatus for recovering a clock signal which is embedded in an incoming data stream is also disclosed.

Abstract: This interconnect chip provides the function of an antifuse device. The interconnect chip is initially disconnected. Application of a high voltage applied across two terminals on the chip causes intrinsic polysilicon, which serves as an insulator between the connections to break down and form a reliable short circuit between the pads by redistribution of impurities from the layers above and below the intrinsic polysilicon.

Abstract: A method and apparatus for generating an output signal in a digitizer. The method includes the steps of generating a first signal when a user contacts a sensor panel wherein the first signal has a first component and a second component, generating a second signal which is substantially identical to the first component of the first signal, and using the second signal to cancel out the first component of the first signal so as to generate the output signal which is substantially identical to the second component of the first signal.

Abstract: An electrically-erasable electrically-programmable read only memory (EEPROM) transistor is programmed and erased by electron tunneling and reduces gate induced drain leakage. The EEPROM transistor comprises a semiconductor substrate having source and drain regions disposed horizontally apart. A floating gate conductor is vertically adjacent to and spaced from the source and drain regions. An insulation layer is disposed between the floating gate conductor and the source and drain regions. A first segment of the insulation layer, which is between the drain region and a minor portion of the floating gate conductor, has a first thickness. A second segment of the insulation layer which is adjacent to the first layer and the remainder on the floating gate conductor, has a second thickness which is substantially greater than the first thickness.

Abstract: A digitizing panel responsive to a signal transmitted from a stylus for generating stylus position information is disclosed. The digitizing panel includes a coordinate generator for determining coordinate data indicative of a position of the stylus relative to the digitizing panel, a velocity calculator for determining a stylus velocity value based on the coordinate data, a mechanism for determining a filter bandwidth value based on the stylus velocity value, a filter for filtering the coordinate data wherein the filter has a predetermined bandwidth characteristic, and a mechanism for varying the predetermined bandwidth characteristic based on the filter bandwidth value. A method for filtering position data of a stylus associated with a digitizing panel is also disclosed.

Abstract: The invention concerns a stylus for producing a high-voltage, sinusoidal signal for an electrostatic digitizing pad. The high voltage is obtained by applying a sine wave to one lead of the primary of a transformer, and applying the inverse of the sine wave to the other lead of the primary. The secondary of the transformer produces the high voltage, which is developed into a signal which is applied to the digitizing pad.

Abstract: Methods and associated apparatus operable in a RAID subsystem to improve the speed and flexibility of initializing the subsystem by storing configuration and identification information in a reserved area on each disk drive in the subsystem. The reserved area on each disk drive of the disk array contains a unique identifier to identify the particular disk drive from all others and further contains group configuration information regarding all groups in which the particular disk drive is a member. The configuration and identification information is generated and written to each disk drive in the disk array when the particular disk drive is configured so as to be added or deleted from groups of the subsystem. Upon subsystem reset (e.g. power on reset or other reset operations), the RAID controller in the subsystem determines the proper configuration of the RAID groups despite temporary unavailability or physical relocation of one or more disk drives in the disk array.

Abstract: The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.

Abstract: A method and apparatus for forming layers of photo-sensitive materials in different thicknesses. A mask including a first area that substantially blocks light transmission and a second area having optical characteristics, which partially blocks light transmission is employed. Light is projected through the mask onto a layer of photo-sensitive material. The first area substantially blocks the light from passing through and leaves portions of the photo-sensitive material unexposed. The secondary area reduces the intensity of light passing through the mask and projected onto other portions of the photo-sensitive material. After developing the photo-sensitive material, at least two thicknesses of photo-sensitive material results. The second area may include a number of sections that vary from each other in optical characteristics such that the intensity of the light projected onto the layer of photo-sensitive material through the second area varies in steps or continuously.

Abstract: A differential receiver that includes a first input, a second input, and an output has a first signal path from the first input to the output, the first signal path including a first differential amplifier and a first active load. The first differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the first active load. The first differential amplifier also has a connection to the first input and the second input, and the first active load has a connection to the output. The receiver also has a second signal path from the second input to the output, the second signal path including a second differential amplifier and a second active load. The second differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the second active load.

Abstract: The clock rate for a device is controlled through the use of integrated circuits which respond to the temperature of the device. Circuitry is added to the integrated circuit device being controlled which changes the clock rate of the device as the device temperature changes. The device clock is thus regulating by the temperature of the device. The way in which the regulation is implemented can be varied, from slowing an internally generated clock rate, or by digitally scaling an external clock input. Synchronous scaling is also provided, such that devices which are connected external to the CPU can still be clocked at the same external rate, but CPU transactions within the CPU may occur at a different rate depending on the CPU's measured temperature. This invention also provides the ability to selectively reduce or stop certain areas of an integrated circuit relative to pending operations or instructions being executed.

Abstract: Circuitry, and an associated method, for a receiver which receives data signals transmitted upon a non-ideal transmission channel. The circuitry includes an equalizer circuit and a variable gain amplifier circuit together operable to counteract the effects of the signal degradation. Characteristics of the equalizer circuit and of the amplifier circuit are together selected responsive to detection of the signal envelope of the data signal.

Abstract: A small buffer called a branch-anticipate buffer (BAB) is used to store groups of instructions which are likely to be required from the instruction cache (I-cache) when an instruction prefetch miss occurs. When a prefetch miss occurs, the BAB is checked to see if instructions corresponding to the target address are available. If they are available, these instructions are copied into an appropriate buffer. If the instructions corresponding to the target address are unavailable, these instructions are fetched from the I-cache and placed into a buffer and, selectively, into the BAB. The BAB only maintains branch target addresses that have not been previously scanned and that cannot be prefetched in time. This allows for smaller buffer sizes, and resulting quicker access time, when checking the BAB for instructions to be executed by a processor.

Abstract: A circuit in a semiconductor device for testing jitter tolerance of a receiver in the semiconductor device. The circuit includes a jitter injection circuit that has an output connected to an input in a phase-locked loop circuit. The jitter injection circuit generates an output signal in response to an application of an input signal. The phase-locked loop circuit has an output that generates a clock signal, wherein the clock signal may be altered by the output signal from the jitter injection circuit. The clock signal from the phase-locked loop circuit controls transmission of data at the transmitter. Alteration of the clock signal caused by the jitter injection circuit alters the manner in which the transmitter transmits data.

Abstract: An apparatus for storing and playing videos. The apparatus includes a storage device containing a video for playback on a user system located on a communications network. The apparatus includes a system connection to a data processing system and a network connection to the communications network. The apparatus includes a transfer means for transferring the video from the storage device to the network using the network connection, wherein the video is directly transferred from the apparatus to the network.

Abstract: Methods and apparatus for the rapid generation of a snapshot copy of the data stored in a RAID storage subsystem. In addition to the users configured RAID logical units, the present invention provides for the definition within the RAID controller of a logical RAID level one device having an operational half comprising the users defined logical unit(s) and having a non-operational mirror component. The user access data stored on the RAID subsystem by direct access to the users defined logical units. When a user directs a snapshot copy request to the operational, user defined logical units, the RAID controller responds by temporarily configuring available storage capacity (e.g. spare disk drives) in the RAID subsystem to perform the function of the non-operational mirror component of the logical RAID level one device.

Abstract: Methods and apparatus for moving pinned data corresponding to a temporarily dead RAID device between the cache memory of a RAID subsystem and a log area. In response to detection of a dead RAID device within a RAID subsystem, the methods of the present invention move any pinned data from the cache memory of the RAID controller to a log area preferably allocated on the disk space of one or more operational RAID devices within the subsystem. In response to revival of the dead RAID device methods of the present invention restore the logged, pinned data from the log area of the operational RAID device(s) to the cache memory as dirty data ready for posting to the revived RAID device. The log area may be either permanently allocated within the RAID subsystem, or may be dynamically allocated in response to recognition of the dead RAID device and freed in response to revival of the RAID device.

Abstract: An arrangement of mounting pads on a substrate having segments, at least one of which has a plurality of mounting pads in a first row. Mounting pads of the first row are in connection with a corresponding offset through-hole oriented outwardly in the same general direction as a bisector definable for that segment, or oriented outwardly in the same general direction as a diagonal of the arrangement's outer shape. The segment defined can have a second and third row of mounting pads. The arrangement could include second, third, fourth, and so on, segments each with a plurality of mounting pads. Also included is an arrangement of Ball Grid Array (BGA) mounting pads on a circuit board for connection with electrical contacts of a BGA package, having: a first segment of a plurality of mounting pads in a first row with each mounting pad of the first row in connection with an offset through-hole oriented outwardly in the same general direction as a bisector definable for that first segment.

Abstract: A bipolar transistor with a relatively deep emitter region is formed in a BICMOS device using the source/drain mask used to form the source and drain regions of MOSFETs of the device and the base region mask which would otherwise be required in any event to diffuse an emitter region of the bipolar transistor. The emitter is diffused or implanted to a depth greater than the depth to which a source and a drain region of the MOSFET are diffused. By using only the base region and source/drain region masks, and developing in sequence, each of two coatings of photoresist applied on top of one another, an access opening to the emitter region is define solely by the co-location of openings in each of the two coatings, thereby allowing the emitter region to be separately and additionally implanted. The access to the base region for the additional implication is achieved using only a few additional photo-ops and not as a result of using an additional emitter mask.

Abstract: A method and associated apparatus for using a content addressable memory (CAM) to process timed events in a process control application. A time value field in each CAM entry identifies the time at which a corresponding event is to be processed. An event identifier field in each CAM entry identifies the event to be processed. A time value generator applies signals indicative of a time value to the CAM. The CAM returns as data on its output signal paths any entries whose time value fields correspond to the applied time value signals. The event identifier field applied to the output signal paths of the CAM is then applied to the process controller to identify an event to be processed. The methods and apparatus of the present invention are applicable, for example, in communication controller devices wherein a protocol requires timed event processing for standardized communications (e.g., Fibre Channel or FDDI).