Abstract: The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.

Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

Abstract: Electric vehicle charging methods, battery charging methods, electric vehicle charging systems, energy device control apparatuses, and electric vehicles are described. In one arrangement, an electric vehicle charging method includes receiving information regarding charging of an electric vehicle with energy from an electric power grid, determining an amount of energy stored by an energy storage device coupled to the electric power grid, and controlling a transfer of the energy stored by the energy storage device to the electric power grid using the information regarding the charging of the electric vehicle. Other arrangements are described.

Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.

Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

Abstract: In one embodiment, a block copolymer-containing composition includes PS-b-PXVP and a lithium salt, where “X” is 2 or 4. All lithium salt is present in the composition at no greater than 1 ppm by weight. In one embodiment, a homogenous block copolymer-including comprising has PS-b-PXVP present in the composition at no less than 99.99998% by weight, where “X” is 2 or 4. Methods of forming such compositions are disclosed.

Abstract: A photolithography monitoring mark on a substrate includes a plurality of sets of lines. Individual of the sets include a plurality of substantially parallel lines comprising different widths arrayed laterally outward in opposing lateral directions from an axial center of the set. The different widths decrease in each of the opposing lateral directions laterally outward from the axial center of the set. Other implementations are disclosed.

Abstract: Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material.

Abstract: A bullet for a firearm includes a rear unit that comprises substantially a solid structure. Additionally, the bullet includes a front unit separate and discrete from the rear unit. The front unit defines a cavity and at least a portion of the rear unit is secured in the cavity of the front unit.

Abstract: Disclosed are hydrocarbon recovery drill string apparatus, subterranean hydrocarbon recovery drilling methods, and subterranean hydrocarbon recovery methods. In one embodiment, a hydrocarbon recovery drill string apparatus includes an elongated assembly within which a rotatable drill rod is received. The assembly comprises a longitudinal axis, a drill rod entrance end, and a drill rod exit end. The assembly comprises a tailcuttings diverter pipe proximate the drill rod exit end, with the tailcuttings diverter pipe defining an initial fluid flow path of the tailcuttings from the longitudinal axis which is acute from the longitudinal axis. Other apparatus and method aspects are contemplated.

Abstract: Enhancement of an image includes adjusting its brightness and then adjusting the contrast of the brightness adjusted image. Adjusting the brightness uses an estimation of real world luminance. Contrast adjustment involves extracting background and contrast information, adjusting the contrast information by an adjustment factor based on the background information and combining the background corrected contrast information to obtain an output image.

Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.

Abstract: A method of lithographically patterning a substrate that has photoresist having removal areas and non-removal areas includes first exposing at least the non-removal areas to radiation effective to increase outer surface roughness of the photoresist in the non-removal areas at least post-develop but ineffective to change photoresist solubility in a developer for the photoresist to be cleared from the non-removal areas upon develop with the developer. Second exposing of radiation to the removal areas is conducted to be effective to change photoresist solubility in the developer for the photoresist to be cleared from the removal areas upon develop with the developer. The photoresist is developed with the developer effective to clear photoresist from the removal areas and to leave photoresist in the non-removal areas that has outer surface roughness in the non-removal areas which is greater than that before the first exposing. Other implementations and embodiments are contemplated.

Abstract: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide -containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.

Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.

Abstract: The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line.

Abstract: Some embodiments include adjustable oral airway devices. The devices may contain a bite block, a tongue deflector extending through the bite block, and at least one locking mechanism configured for releasably retaining the tongue deflector in one of two or more predetermined positions within the bite block. Some embodiments include adjustable oral airway kits. Such kits may contain a bite block, a tongue deflector configured to extend within an opening in the bite block, and at least one locking mechanism configured for releasably retaining the tongue deflector in one of two or more predetermined positions within the bite block.

Abstract: The present invention relates to a process for recovery and purification of lactic acid from a fermentation broth containing lactic acid. The process comprises subjecting the fermentation broth to ultrafiltration and/or microfiltration to form a first permeate, concentrating the first permeate to form concentrated broth, subjecting the concentrated broth to supported liquid membrane for extraction of lactic acid into a separate stream, subjecting the extracted lactic acid solution to activated carbon for removal of color, subjecting the extracted lactic acid solution to cation exchange resin for deminerization, subjecting the extracted lactic acid solution to anion exchange resin for removal of anionic impurities and concentrating the extracted lactic acid solution to desired concentration. The supported liquid membrane of the present invention contains an organic layer that comprises a earner, a co-extractant, a diluent and a stabilizer.

Abstract: Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

Abstract: Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed along sidewalls of the first features, and third material is formed over the second material and the first features. The third material may be formed at a temperature above the reflow temperature of the first material, and the second material may support the first features so that the first features do not collapse even though they are exposed to such temperature. In some embodiments the third material has an undulating topography. Fourth material may be formed within the valleys of the undulating topography, and subsequently the first features may be removed together with at least some of the third material to leave a pattern comprising second features formed from the second material and pedestals formed from the fourth material.