Abstract: Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic block copolymers can undergo microphase separation.

Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.

Abstract: The invention includes a device having a chamber within a syringe. A fluid passageway extends through a syringe piston. A valve is associated with the passageway controlling fluid passage through the piston. The invention includes a piercing structure having a head segment and a body portion, with a channel through the body portion and through at least one surface of the head without passing through the tip. In another aspect the invention encompasses a method of preparing an agent for administration to an individual. A first component is provided within a syringe and a second component is provided within a vial. A closed valve is associated with a fluid passageway between the vial and the syringe barrel through a piston. Valve repositioning allows fluid passage and sliding of the piston joins the first and second components. Repeated sliding of the piston mixes the components to produce the medication agent.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: Uninterruptible power supplies, solar power kits for uninterruptible power supplies and related methods are described. According to one aspect, an uninterruptible power supply includes a power bus, mains circuitry configured to rectify electrical energy received from a mains supply system into rectified electrical energy and to provide the rectified electrical energy to a power bus of the uninterruptible power supply, photovoltaic circuitry configured to convert solar energy into converted electrical energy and to provide the converted electrical energy to the power bus, a battery system configured to receive electrical energy from the power bus to charge a battery of the battery system and to discharge electrical energy to the power bus, an inverter configured to provide electrical energy from the power bus to the load, and a controller configured to monitor the photovoltaic circuitry and to implement at least one operation of the uninterruptible power supply using the monitoring.

Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.

Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Abstract: A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.

Abstract: Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A second sacrificial material may be formed over the first capacitor storage node and over the first sacrificial material, and a retaining structure may be formed over the second sacrificial material. A second opening may be formed through the retaining structure and the second sacrificial material, and a second capacitor storage node may be formed within the second opening and against the first storage node. The first and second sacrificial materials may be removed, and then capacitor dielectric material may be formed along the first and second storage nodes. Capacitor electrode material may then be formed along the capacitor dielectric material. Some embodiments include methods of forming DRAM unit cells, and some embodiments include DRAM unit cell constructions.

Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.

Abstract: A method of forming a transistor gate construction includes forming a gate stack comprising a sacrificial material received over conductive gate material. The gate stack has lateral sidewalls having insulative material received there-against. The sacrificial material is removed from being received over the conductive gate material to form a void space between the insulative material over the conductive gate material. Elemental tungsten is selectively deposited within the void space over the conductive gate material and a transistor gate construction forming there-from is formed there-from, and which has a conductive gate electrode which includes the conductive gate material and the elemental tungsten. The transistor gate might be used in NAND, DRAM, or other integrated circuitry.

Abstract: In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which contain steep sidewalls joining to one another at shallow sidewall regions. The constructions may also contain lines along and directly against the steep sidewalls, and spaced from one another by gaps along the shallow sidewall regions.

Abstract: The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.

Abstract: Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening.

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material.

Abstract: Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 ?/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.

Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.