Patents Represented by Law Firm Wells, St. John & Roberts
  • Patent number: 6357680
    Abstract: A comminuting apparatus includes a frame, a set of overlapping scissor rolls, a first drive motor, and a second drive motor. The frame has an enclosure with an entrance opening for receiving waste material. The set of overlapping scissor rolls is carried within the enclosure for rotation, including a first scissor roll and a second scissor roll. The first drive motor is coupled to the first scissor roll, and the second drive motor is coupled to the second scissor roll. The first drive motor is operative to drive the first scissor roll at a substantially variable operating speed. The second drive motor is operative to drive the second scissor roll in co-rotation at a substantially constant operating speed.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: March 19, 2002
    Inventor: Jere F. Irwin
  • Patent number: 6355966
    Abstract: A method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench. In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: March 12, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Jigish D. Trivedi
  • Patent number: 6355299
    Abstract: The invention encompasses methods of forming insulating materials proximate conductive elements. In one aspect, the invention includes a method of forming an insulating material proximate a substrate comprising: a) chemical vapor depositing a first material proximate a substrate; b) forming cavities within the first material; and c) after forming cavities within the first material, transforming at least some of the first material into an insulative second material. In another aspect, the invention includes a method of forming an insulating material proximate a substrate comprising: a) forming porous polysilicon proximate a substrate; and b) transforming at least some of the porous polysilicon into porous silicon dioxide.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: March 12, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6355985
    Abstract: The present invention includes integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device. According to one aspect of the present invention, an integrated circuit device includes a semiconductor die and a first housing encapsulating the semiconductor die. A heat sink is positioned proximate the first housing and a second housing is formed to encapsulate at least a portion of the heat sink. The heat sink is preferably thermally coupled with the semiconductor die and configured to expel heat therefrom. Another aspect provides a method of forming an integrated circuit device including the steps of providing a semiconductor die; forming a first housing about the semiconductor die; thermally coupling a heat sink with the first housing; and forming a second housing about at least a portion of the heat sink following the thermally coupling.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: March 12, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Brand
  • Patent number: 6356495
    Abstract: A dynamic random access memory includes a plate line; a digit line; a memory cell selectively coupled between the digit line and the plate line; sense circuitry selectively coupled to the memory cell to read the memory cell and capable of applying a first voltage from the plate line to the digit line; equilibration circuitry selectively coupling the plate line to an equilibration voltage less than the first voltage and selectively coupling the digit line to the equilibration voltage; and control circuitry configured to cause the equilibration circuitry to couple the plate line to the equilibration voltage while the memory cell is being accessed. A method of manufacturing a dynamic random access memory includes providing control circuitry configured to operate in a specified manner.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: March 12, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Tyler A. Lowrey
  • Patent number: 6352932
    Abstract: In one aspect, a plurality of layers are formed over a substrate and a series of first trenches are etched into a first of the layers in a first direction. A series of second trenches are etched into the first layer in a second direction which is different from the first direction. Collectively, the first and second trenches define a plurality of different substrate elevations with adjacent elevations being joined by sidewalls which extend therebetween. Sidewall spacers are formed over the sidewalls, and material of the first layer is substantially selectively etched relative to material from which the spacers are formed. Material comprising the spacer material is substantially selectively etched relative to the first material. In a preferred implementation, the etching provides a plurality of cells which are separated from one another by no more than a lateral width dimension of a previously-formed spacer.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: March 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, James E. Green
  • Patent number: 6353241
    Abstract: Methods of forming conductive lines and insulative spacers thereover are described. In accordance with one aspect of the invention, a substrate is provided having a first area and a second area relative to which conductive lines are to be formed. A layer of conductive material is formed over the first and second substrate areas and a layer of insulative material is formed over the conductive material. In a preferred implementation, insulative material is removed from the second area and conductive lines are subsequently patterned and etched in both the first and second areas. In another preferred implementation, conductive lines are first patterned and etched with insulative material in the second area being subsequently removed. The patterned and etched conducted lines have respective sidewalls.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: March 5, 2002
    Assignee: Micron Technology, Inc.
    Inventor: H. Montgomery Manning
  • Patent number: 6352933
    Abstract: In one aspect, the invention encompasses a method of forming an insulating material around a conductive component. A first material is chemical vapor deposited over and around a conductive component. Cavities are formed within the first material. After the cavities are formed, at least some of the first material is transformed into an insulative second material. In another aspect, the invention encompasses a method of forming an insulating material. Polysilicon is deposited proximate a substrate. A porosity of the polysilicon is increased. After the porosity is increased, at least some of the polysilicon is transformed into silicon dioxide.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: March 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6350093
    Abstract: An electrically insulated anchor device is described, comprising a rigid elongated metal sleeve including an external surface that leads from an open top end to a bottom end. A longitudinal internal bore is formed within the sleeve with a bore wall spaced from the external surface by a sleeve wall thickness dimension. An electrically insulative polymer insert with an external surface engages the bore wall within the sleeve. The insert further includes a fastener receiving bore defined by a fastener receiving wall spaced from the external insert surface by an insert wall thickness dimension. The sleeve wall thickness dimension is substantially greater than the insert wall thickness dimension.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: February 26, 2002
    Assignee: CXT Incorporated
    Inventors: Rick W. Petersen, Steven R. Mattson
  • Patent number: 6350638
    Abstract: A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate w
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Charles H. Dennison
  • Patent number: 6351038
    Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Patent number: 6351190
    Abstract: A stage for a voltage controlled oscillator includes a first p-channel transistor having a gate defining a control node, having a source adapted to be coupled to a supply voltage, and having a drain; a second p-channel transistor having a gate coupled to the control node, having a source coupled to the supply voltage, and having a drain; a first n-channel transistor having a gate defining a first input, having a drain coupled to the drain of the first p-channel transistor and defining a first node, and having a source; a second n-channel transistor having a gate defining a second input, having a drain coupled to the drain of the second p-channel transistor and defining a second node, and having a source; a current draw; first and second loads; a first source follower having an input coupled to the first node; and a second source follower.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventors: James E. O'Toole, John R. Tuttle, Mark E. Tuttle, Tyler Lowrey, Kevin M. Devereaux, George E. Pax, Brian P. Higgins, Shu-Sun Yu, David K. Ovard, Robert R. Rotzoll
  • Patent number: 6351630
    Abstract: A wireless communications system comprising a first transponder adapted to be coupled to one of a plurality of selectable antennas, having a look-up table including locations holding data representing antennas, and having pointers pointing to selected ones of the locations, the pointers defining an order in which antennas will be used to attempt communication; and a second transponder configured to communicate with the first transponder, wherein the first transponder uses an antenna defined by data in one location of the table for communication with the second transponder, and, if successful communication with the second transponder is not established, the first transponder uses an antenna defined by data in another location of the table selected in accordance with the order defined by the pointers.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Clifton W. Wood, Jr.
  • Patent number: 6350679
    Abstract: The invention comprises methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry. In one implementation, a method of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry includes forming a conductive metal interconnect layer over a substrate. An insulating dielectric mass is provided about the conductive metal interconnect layer. The insulating dielectric mass has a first dielectric constant. At least a majority of the insulating dielectric mass is etched away from the substrate. After the etching, an interlevel dielectric layer is deposited to replace at least some of the etched insulating dielectric material. The interlevel dielectric layer has a second dielectric constant which is less than the first dielectric constant.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Terrence McDaniel, Max F. Hineman
  • Patent number: 6349902
    Abstract: A windsock includes an elongated fuselage with outwardly extending dihedral wings. A dihedral spar extends along the wings and is joined with a coupling that is movably positioned within the fuselage cavity. A stabilizer is also mounted to the coupling and is movable within the fuselage through a limited range of motion.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: February 26, 2002
    Inventor: Jeffrey Ray Cripe
  • Patent number: 6348003
    Abstract: Disclosed is a tap driver for rigid tapping, which includes predetermined tension and compression factors to self-synchronize the tap driver. In the preferred embodiment, the tap driver includes helical coils imparted in the tap driver body which allow the attachment body to synchronize axially in response to a force of a predetermined magnitude imparted on the tap. An additional embodiment of this invention provides such a tap driver body wherein the body allows for lateral flexure and movement to compensate for feed error and location error.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: February 19, 2002
    Assignee: Tapmatic Corporation
    Inventors: Allan S. Johnson, Mark F. Johnson
  • Patent number: 6348139
    Abstract: Described is the production of a metal article with fine metallurgical structure and texture by a process that includes forging and rolling and control of the forging and rolling conditions. Also described is a metal article with a minimum of statically crystallized grain size and a uniform (100) cubic texture.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: February 19, 2002
    Assignee: Honeywell International Inc.
    Inventors: Ritesh P. Shah, Vladimir Segal
  • Patent number: 6348882
    Abstract: A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: February 19, 2002
    Assignee: Philips Electronics North America Corporation
    Inventors: John Charles Ciccone, D.C. Sessions, Carl Liepold
  • Patent number: PP12415
    Abstract: A new and distinct variety of apple tree (Malus Pumila Mill) named ‘Nevson,’ and which is characterized as to novelty by uniqueness of shape, color, flavor and texture, and a date of maturity for commercial harvesting and shipment of approximately September 10 through October 1 under the ecological conditions prevailing in the Columbia Basin area of Central Washington.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: February 19, 2002
    Assignee: Nevis Fruit Company LTD
    Inventor: John McLaren
  • Patent number: D454263
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: March 12, 2002
    Inventor: Raymond Worrall