Patents Represented by Law Firm Wells, St. John & Roberts
  • Patent number: 6338938
    Abstract: In one aspect the invention includes a method of forming a semiconductor device, comprising: a) forming a layer over a substrate; b) forming a plurality of openings extending into the layer; c) depositing particles on the layer; d) collecting the particles within the openings; and e) using the collected particles as a mask during etching of the underlying substrate to define features of the semiconductor device. In another aspect, the invention includes a method of forming a field emission display, comprising: a) forming a silicon dioxide layer over a conductive substrate; b) forming a plurality of openings extending into the silicon dioxide layer; c) depositing particles on the silicon dioxide layer; d) collecting the particles within the openings; e) while using the collected particles as a mask, etching the conductive substrate to form a plurality of conically shaped emitters from the conductive substrate; and f) forming a display screen spaced from said emitters.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: January 15, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Eric A. Lahaug
  • Patent number: 6337243
    Abstract: A semiconductor processing method of providing a hemispherical grain polysilicon layer atop a substrate includes, a) providing a substantially amorphous layer of silicon over a substrate at a selected temperature; b) raising the temperature of the substantially amorphous silicon layer to a higher dielectric layer deposition temperature, the temperature raising being effective to transform the amorphous silicon layer into hemispherical grain polysilicon; and c) depositing a dielectric layer over the silicon layer at the higher dielectric deposition temperature. Transformation to hemispherical grain might occur during the temperature rise to the higher dielectric layer deposition temperature, after the higher dielectric layer deposition temperature has been achieved but before dielectric layer deposition, or after the higher dielectric layer deposition temperature has been achieved and during dielectric layer deposition.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Er-Xang Ping, Randhir P. S. Thakur
  • Patent number: 6337244
    Abstract: A method of forming a line of FLASH memory cells includes forming a first line of floating gates over a crystalline silicon semiconductor substrate. An alternating series of SiO2 isolation regions and active areas are provided in the semiconductor substrate in a second line adjacent and along at least a portion of the first line of floating gates. The series of active areas define discrete transistor source areas. A masking layer is formed over the floating gates, the regions and the areas. A third line mask opening is formed in the masking layer over at least a portion of the second line. Anisotropic etching is conducted of the SiO2 isolation regions exposed through the third line mask opening substantially selectively relative to crystalline silicon exposed through the third line mask opening using a gas chemistry comprising a combination of at least one non-hydrogen containing fluorocarbon having at least three carbon atoms and at least one hydrogen containing fluorocarbon.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Guy T. Blalock
  • Patent number: 6337634
    Abstract: A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: James E. O'Toole, John R. Tuttle, Mark E. Tuttle, Tyler Lowrey, Kevin M. Devereaux, George E. Pax, Brian P. Higgins, David K. Ovard, Shu-Sun Yu, Robert R. Rotzoll
  • Patent number: 6337237
    Abstract: A capacitor processing method includes forming a capacitor comprising first and second electrodes having a capacitor dielectric region therebetween. The first electrode interfaces with the capacitor dielectric region at a first interface. The second electrode interfaces with the capacitor dielectric region at a second interface. The capacitor dielectric region has a plurality of oxygen vacancies therein. After forming the capacitor, an electric field is applied to the capacitor dielectric region to cause oxygen vacancies to migrate towards one of the first and second interfaces. Oxygen atoms are preferably provided at the one interface effective to fill at least a portion of the oxygen vacancies in the capacitor dielectric region. Preferably at least a portion of the oxygen vacancies in the high k capacitor dielectric region are filled from oxide material comprising the first or second electrode most proximate the one interface.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej S. Sandhu
  • Patent number: 6336477
    Abstract: In a weaving device, a weaving device frame mounts a plurality of eyelets. A frame module, releasably borne by the weaving device frame is readily detachable from and controls movement of the respective eyelets. The frame module forms a readily removable component of the weaving device.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: January 8, 2002
    Assignee: WIS Seaming
    Inventors: Chester F. Kutzleb, Roger King, Anders Bostrom, Robert Kellogg
  • Patent number: 6337575
    Abstract: A method of testing integrated circuitry includes providing a substrate comprising integrated circuitry to be tested. The circuitry substrate to be tested has a plurality of exposed conductors in electrical connection with the integrated circuitry. In one implementation, at least some of the exposed conductors of the circuitry substrate are heated to a temperature greater than 125° C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductors of the circuitry substrate. In one implementation, such are heated to a temperature below their melting temperature yet effective to soften said at least some of the exposed conductors to a point enabling their deformation upon application of less than or equal to 30 grams of pressure per exposed conductor. The circuitry substrate is engaged with a tester substrate.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6337261
    Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 6337274
    Abstract: The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Pai-Hung Pan, Scott Jeffrey DeBoer
  • Patent number: 6335049
    Abstract: A chemical vapor deposition method of forming a high k dielectric layer includes positioning a substrate within a chemical vapor deposition reactor. At least one metal comprising precursor and N2O are provided within the reactor under conditions effective to deposit a high k dielectric layer on the substrate comprising oxygen and the metal of the at least one metal precursor. The N2O is present within the reactor during at least a portion of the deposit at greater than or equal to at least 90% concentration by volume as compared with any O2, O3, NO, and NOX injected to within the reactor. In one implementation, the conditions are void of injection of any of O2, O3, NO, and NOX to within the reactor during the portion of the deposit. In one implementation, a capacitor is formed using the above methods. In preferred implementations, the technique can be used to yield smooth, continuous dielectric layers in the absence of haze or isolated island-like nuclei.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: January 1, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Cem Basceri
  • Patent number: 6335237
    Abstract: The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one conductive material. Openings are etched through the bitline layer and to the electrical nodes. After the openings are formed, the bitline layer is patterned into bitlines. The invention also encompasses a method of forming a capacitor and bitline structure. A substrate is provided, and comprises a plurality of spaced electrical nodes. A stack of bitline materials is formed over at least some of the spaced electrical nodes. The bitline materials comprise at least one insulative material over at least one conductive material. Openings are etched through the bit line materials and to the electrical nodes. Conductive masses are formed in at least some of the openings. After the conductive masses are formed, the bitline materials are patterned into bitlines.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: January 1, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Raj Narasimhan
  • Patent number: 6335254
    Abstract: In accordance with an aspect of the invention, a transistor is formed having a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes at least two conductive layers of different conductive materials. One of the two conductive layers is more proximate the gate dielectric layer than the other of the two conductive layers. A source/drain reoxidation is conducted prior to forming the other conductive layer. In another aspect of the invention, a transistor has a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes a tungsten layer. A source/drain reoxidation is conducted prior to forming the tungsten layer of the gate. In yet another aspect of the invention, a semiconductor processing method forms a transistor gate having insulative sidewall spacers thereover. After forming the insulative sidewall spacers, an outer conductive tungsten layer of the transistor gate is formed.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: January 1, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Jigish D. Trivedi
  • Patent number: 6335282
    Abstract: The invention includes methods of forming titanium comprising layers, and methods of forming conductive silicide contacts. In one implementation, a method of forming a titanium comprising layer includes chemical vapor depositing a layer a majority of which comprises elemental titanium, titanium silicide or a mixture thereof over a substrate using a precursor gas chemistry comprising titanium and chlorine. The layer comprises chlorine from the precursor gas chemistry. The layer is exposed to a hydrogen containing plasma effective to drive chlorine from the layer. In one implementation, a method of forming a conductive silicide contact includes forming an insulating material over a silicon comprising substrate. An opening is formed into the insulating material over a node location on the silicon comprising substrate to which electrical connection is desired. A layer is chemical vapor deposited over the substrate using a precursor gas chemistry comprising titanium and chlorine.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: January 1, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Sujit Sharan, Gurtej S. Sandhu
  • Patent number: 6335270
    Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: January 1, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Pai-Hung Pan, Luan C. Tran, Tyler A. Lowrey
  • Patent number: 6333539
    Abstract: In one aspect, the invention encompasses a transistor device comprising a region of a semiconductor material wafer, and a transistor gate over a portion of the region. The transistor gate has a pair of opposing sidewalls which are a first sidewall and a second sidewall. The device further comprises a pair of opposing sidewall spacers adjacent the sidewalls of the transistor gate and a pair of opposing first conductivity type source/drain regions within the semiconductor material wafer proximate the transistor gate. One of the sidewall spacers extends along the first sidewall of the gate and the other of the sidewall spacers extends along the second sidewall of the gate. The entirety of the semiconductor wafer material under one of the sidewall spacers being defined as a first segment of the semiconductor wafer material, and the entirety of the semiconductor wafer material which is under the other of the sidewall spacers being defined as a second segment of the semiconductor wafer material.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Aftab Ahmad, David J. Keller
  • Patent number: 6333256
    Abstract: The invention includes a semiconductor processing method which comprises forming a first material layer over a substrate. A second material layer is formed over the first material layer. Photoresist is deposited over the second material layer, and an opening is formed within the photoresist to the second material layer. The second material layer is etched through the photoresist opening to a degree insufficient to outwardly expose the first material layer. The photoresist is then stripped from the substrate. Subsequently, the second material layer and the first material layer are blanket etched.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Shubneesh Batra
  • Patent number: 6333264
    Abstract: In accordance with one aspect of the invention, a semiconductor processing method of treating a semiconductor wafer provides a wafer within a volume of liquid. The wafer has some electrically conductive material formed thereover. The volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere and at a temperature of at least 200° C., and below and within 10% of the melting point of the electrically conductive material. In accordance with another aspect, the volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere. After establishing the pressure of greater than 1 atmosphere, the pressure of the volume of liquid is lowered to a point effective to vaporize said liquid and the vapor is withdrawn from the chamber.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, Mark Durcan
  • Patent number: 6333225
    Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Klaus Florian Schuegraf, Randhir P. S. Thakur
  • Patent number: 6333693
    Abstract: The present invention provides wireless communication and identification packages, communication systems, methods of identifying an identification device, methods of communicating, and methods of forming a communication device. In one aspect of the present invention, a wireless communication package includes a communication device having a substrate; communication circuitry borne by the substrate, the communication circuitry being configured to at least one of process and form wireless communication signals; and at least one antenna electrically coupled with the communication circuitry, the antenna being configured to at least one of receive wireless communication signals and output wireless communication signals; and an appendage coupled with the communication device, the appendage being configured to enhance at least one of receiving and outputting of wireless communication signals via the antenna.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Freddie W. Smith
  • Patent number: D452548
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: December 25, 2001
    Inventor: John A. Bambacigno