Patents Represented by Law Firm Wells, St. John & Roberts
  • Patent number: 6333254
    Abstract: In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Todd R. Abbott, Michael P. Violette, Charles H. Dennison
  • Patent number: 6333556
    Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Werner Juengling, Kirk D. Prall, Ravi Iyer, Gurtej S. Sandhu, Guy Blalock
  • Patent number: 6331725
    Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: December 18, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 6331461
    Abstract: Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: December 18, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 6329267
    Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: December 11, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David L. Dickerson, Richard H. Lane, Charles H. Dennison, Kunal R. Parekh, Mark Fischer, John K. Zahurak
  • Patent number: 6329453
    Abstract: A photochromic phase change ink composition that contains (A) at least one selected polymeric and photochromic yellow phase change colorant and (B) a phase change ink carrier composition comprising (1) a resin selected from the group consisting of a urethane resin, a mixed urethane/urea resin and mixtures thereof; and (2) a mono-amide.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: December 11, 2001
    Assignee: Xerox Corporation
    Inventors: Michael B. Meinhardt, Randall R. Bridgeman
  • Patent number: 6329213
    Abstract: The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of forming an integrated circuit within a substrate comprising: a) providing a recess in a substrate; b) printing an antenna within the recess; and c) providing an integrated circuit chip and a battery in electrical connection with the antenna.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: December 11, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Rickie C. Lake
  • Patent number: 6326250
    Abstract: In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second trans
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: December 4, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Aftab Ahmad, Kirk Prall
  • Patent number: 6327513
    Abstract: Methods and apparatus for calculating alignment of layers during semiconductor processing are described. In one embodiment, first and second alignment targets are formed over a substrate and include respective pairs of first and second alignment target edges. The second alignment target defines a point of reference. First and second distances are measured between the first alignment target edges and the second alignment target edges as respective first and second functions of the distance from the point of reference. The first and second functions are differenced to define a linear equation having a slope and an intercept which contains offset components in two different directions. In a preferred embodiment, third and fourth alignment targets are formed over the substrate, with the fourth alignment target defining a different point of reference.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: December 4, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: David Ziger
  • Patent number: 6326321
    Abstract: In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: December 4, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Scott Jeffrey DeBoer, John T. Moore, Mark Fischer, Randhir P. S. Thakur
  • Patent number: 6323104
    Abstract: A method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench. In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Jigish D. Trivedi
  • Patent number: 6323540
    Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Charles H. Dennison
  • Patent number: 6323080
    Abstract: The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Kunal R. Parekh
  • Patent number: 6324211
    Abstract: The present invention includes interrogators, communication systems, communication methods, and methods of processing a communication signal. One aspect of the present invention provides a backscatter system interrogator including a downconverter configured to receive a backscatter communication signal having a first frequency and convert the backscatter communication signal having the first frequency to a subcarrier signal having a second frequency less than the first frequency; a filter coupled with the downconverter and configured to filter direct path energy from the subcarrier signal; and a gain control coupled with the filter and configured to adjust the gain of the filtered subcarrier signal.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David K. Ovard, Roy Greeff
  • Patent number: 6323772
    Abstract: The invention encompasses a living organism sensing device. Such device comprises a conductive loop extending over a substrate. The loop comprises carbon particles. The device further comprises a circuit which includes the conductive loop as a first circuit component and a transponder as a second circuit component. The transponder is configured to emit a first signal if the loop of conductive material is continuous and a second signal if the loop of conductive material is broken. The second signal is different than the first signal. The invention also encompasses a termite sensing device. Such device includes at least one wooden block, and a conductive loop proximate the wooden block. The loop comprises conductive particles of carbon. The termite sensing device further includes an electrical circuit comprising the conductive loop as a first circuit component and a transponder as a second circuit component.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Rickie C. Lake
  • Patent number: 6323087
    Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 6323139
    Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventors: John T. Moore, Scott Jeffrey DeBoer, Mark Fischer, J. Brett Rolfson, Annette L. Martin, Ardavan Niroomand
  • Patent number: 6319644
    Abstract: Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: November 20, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Christophe Pierrat, James E. Burdorf, William Baggenstoss, William Stanton
  • Patent number: D450985
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: November 27, 2001
    Inventor: Gary Lynn Kiehl
  • Patent number: D451055
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: November 27, 2001
    Inventor: Ernest John Wilmot