Patents Represented by Attorney, Agent or Law Firm William D. Sabo
  • Patent number: 7473970
    Abstract: An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Jeffrey S. Brown, David M. Fried, Robert J. Gauthier, Jr., Edward J. Nowak, Jed H. Rankin, William R. Tonti
  • Patent number: 7436211
    Abstract: The present invention provides a transparent latch circuit capable of performing a scan test in general scan design (GSD). In the transparent latch circuit a test signal is at a Low level during normal operation. Since a latch stop circuit outputs a High-level latch stop signal, a slave latch circuit has a received signal pass through it directly and a master latch circuit operates as a latch circuit in response to a signal output from an inverter. On the other hand, a test signal is at a High level during scan test. At this point, the latch stop circuit outputs a signal complementary to the signal output from the inverter. Therefore, the master latch circuit and the slave latch circuit operate as latch circuits responding to signals complementary to each other. Thereby, the entire transparent latch circuit operates as a flip-flop circuit.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventor: Makoto Ueda
  • Patent number: 7291568
    Abstract: A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: November 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Bernie A. Roque, Jr., Steven M. Shank, Beth A. Ward
  • Patent number: 7285474
    Abstract: Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, the dielectric layer; forming a sacrificial layer on opposing sidewalls of the trench; filling the trench with a electrical conductor; and removing a portion of the sacrificial layer from between the electrical conductor and the dielectric layer to form air-gaps.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: October 23, 2007
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Jeffrey P. Gambino, Anthony K. Stamper
  • Patent number: 7098083
    Abstract: A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventors: John A. Fifield, Russell J. Houghton, William R. Tonti
  • Patent number: 7052958
    Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having Non-Volatile Random Access Memory (NVRAM) capability. NVRAM capability arises from the presence of double floating gates arranged on and insulated from a semiconductor fin body, and a control gate arranged on and insulated from the double floating gates.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 30, 2006
    Assignee: International Business Machines Corporation
    Inventors: David M. Fried, Chung Hon Lam, Edward J. Nowak
  • Patent number: 7041581
    Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming a non-dopant region near the edge of a dopant region. The preferred embodiment method to increase the latch-up immunity of CMOS devices uses hybrid photoresist to selectively form non-dopant implants near the edges of the N-well and/or P-well. The non-dopant implants suppress diffusion of dopant in the wells resulting in greater control of well spacing, and hence reducing the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows the non-dopant implants to be formed without requiring additional masking steps over the prior art methods.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: May 9, 2006
    Assignee: International Business Machines Corporation
    Inventors: Steven H. Voldman, Louis D. Lanzerotu
  • Patent number: 6982227
    Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: January 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Robert M. Geffken, Vincent J. McGahay, William T. Motsiff, Mark P. Murray, Amanda L. Piper, Anthony K. Stamper, David C. Thomas, Christy S. Tyberg, Elizabeth T. Webster
  • Patent number: 6958506
    Abstract: Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: October 25, 2005
    Assignee: International Business Machines Corporation
    Inventors: Evgeni P. Gousev, Harald F. Okorn-Schmidt, Arne W. Ballantine, Douglas A. Buchanan, Eduard A. Cartier, Douglas D. Coolbaugh
  • Patent number: 6940130
    Abstract: A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Andres Bryant, Peter E. Cottrell, John J. Ellis-Monaghan, Robert J. Gauthier, Jr., Edward J. Nowak, Jed H. Rankin, Fariborz Assaderaghi
  • Patent number: 6919277
    Abstract: Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: July 19, 2005
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak
  • Patent number: 6884734
    Abstract: A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: April 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Frederick W. Buehrer, Derek Chen, William Chu, Scott Crowder, Sadanand V. Deshpande, David V. Horak, Wesley C. Natzle, Hung Y. Ng, Len Y. Tsou, Chienfan Yu
  • Patent number: 6835973
    Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low &kgr; nanopore/nanofoam dielectric material adjacent the conductive line ends.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: December 28, 2004
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, William A. Klaasen, William T. Motsiff, Rosemary A. Previti-Kelly, Jed H. Rankin
  • Patent number: 6833299
    Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: December 21, 2004
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, James Stuart Dunn, Stephen Arthur St. Onge
  • Patent number: 6833720
    Abstract: Electrical detection is provided for dicing damage to moisture barrier/edge seals of IC chips which include a low-K dielectric material, a moisture barrier/edge seal for the IC chip, and a moisture damage sensor circuit positioned on the IC chip in proximity to the moisture barrier/edge seal. One or a plurality of moisture barrier/edge seals can be positioned along peripheral edges of the IC chip, and one or more moisture damage sensor circuit(s) can be positioned between the plurality of moisture barrier/edge seal(s), or between an active area of the IC chip and the moisture barrier/edge seal(s), or on a peripheral area of the IC chip outside of the moisture barrier/edge seal(s).
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: December 21, 2004
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Thomas L. McDevitt, Anthony K. Stamper
  • Patent number: 6827868
    Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: December 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, William T. Motsiff
  • Patent number: 6822472
    Abstract: A detection system and method including a means for performing a test on a semiconductor device and obtaining test data therefrom. The semiconductor device includes an insulating layer, a hard mask layer on a surface of the insulating layer, and a plurality of electrically conductive lines within a trench in the insulating layer. The insulating layer comprises a first dielectric material. The hard mask layer comprises a second dielectric material. The dielectric constant of the second dielectric material exceeds the dielectric constant of the first dielectric material or the second dielectric material comprises an element that is not comprised by the first dielectric material. The test data is a function of a spatial distribution of the hard mask layer on the surface of the insulating layer. The detection system and method includes a means for determining from the test data a measure of the spatial distribution of the hard mask layer on the surface of the insulating layer.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Sanjit K. Das, Anthony K. Stamper, Eric J. White
  • Patent number: 6818992
    Abstract: A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: November 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Douglas S. Armbrust, Margaret L. Gibson, Laura Serianni, Eric J. White
  • Patent number: 6818487
    Abstract: A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: November 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Jack Allan Mandelman, William Robert Tonti, Li-Kong Wang
  • Patent number: 6815838
    Abstract: A laser alignment target is provided having a surface that is out of plane with and has substantially the same first reflectivity as an adjacent surface of the semiconductor device, and a sidewall having a second reflectivity different than the first reflectivity. The target provides sidewalls that provide contrast for finding the target despite loss of contrast created by layers of dielectric over the target and use of short wavelength light.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Richard A. Gilmour, William T. Motsiff, Christopher D. Muzzy