Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.

Abstract: A system and method of monitoring and predicting tool overlay settings comprise generating current lot information, generating historical data, categorizing (binning) the historical data into discrete exposure field size ranges, and predicting current lot tool overlay settings based on the current lot information and historical data. The method monitors the overlay errors during each lot pass through each lithographic process operation. Moreover, the method uses a feedback sorting criteria to monitor the tool overlay settings. Furthermore, the current lot information comprises lithographic field dimensions, wherein the lithographic field optics distortion data is derived from the current lithographic process tool. Additionally, the historical data comprises same-bin lithographic field size dimensions of previous lots, which statistically means the data is derived from the same (or similar) bin of like lots, on the current lithographic process tool.

Abstract: A method of forming a Fin structure including a resistor present in the thin vertically oriented semiconductor body is provided. The method includes the steps of forming at least one vertically-oriented semiconductor body having exposed vertical surfaces on a substrate; implanting dopant ions into the exposed vertical surfaces of the at least one semiconductor body off-axis at a concentration and energy sufficient to penetrate into the exposed vertical surfaces of the at least one semiconductor body without saturation; and forming contacts to the at least one semiconductor body. The present invention is directed to a Fin structure which includes a resistor present within the thin vertically oriented semiconductor body.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film.

Abstract: A method and system for determining overlay tolerances. The method comprises the steps of exposing wafers at different critical dimensions (preferably, above, below, and at optimum image size); and varying the overlay across each wafer, preferably by intentionally increasing the magnification. Functional yield data are used to determine the overlay tolerance for each of the image sizes. The present invention, thus, studies the interaction of image size and feature misalignment. Prior to this invention, the only way to attain this information was to process a large number of lots and create a trend of image size and alignment vs. yield. The present invention solves the problem by determining the overlay tolerance based on yield data from a single lot. The design can then be altered or the overlay limit can be tightened (or relaxed) based on failure analysis of the regions/features that are most sensitive to misalignment.

Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminants on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminants on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.

Abstract: A method of providing a substantially planar trench isolation region having substantially rounded corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a nitride layer; (b) patterning said film stack to form at least one trench within said substrate, wherein said patterning exposes sidewalls of said oxide layer, polysilicon layer and nitride layer; (c) oxidizing the at least one trench and said exposed sidewalls of said oxide layer and said polysilicon layer so as to thermally grow a conformal oxide layer in said trench and on said exposed sidewalls of said oxide layer and said polysilicon layer; (d) filling said trench with a trench dielectric material; and (e) planarizing to said surface of said substrate.

Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract: A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: A method and system embodying the present invention for predicting systematic overlay affects in semiconductor lithography. This method is a feed-forward method, based on correlation of current and prior aligned levels, to predict optimum overlay offsets for a given lot. Instead of using population averaging, which ignores process variability, it acknowledges the variability and uses prior measurements to advantage. The principle, backed by production data, is that “systematic” overlay errors are just that: Image placement errors which persist through processing and will be predictable through time and processing.

Abstract: The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

Abstract: A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligned to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the N-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.

Abstract: A method and system for measuring lithographic image foreshortening. The method comprises the steps of providing a critical dimension scanning electron microscope, and using that critical dimension scanning electron microscope to measure lithographic image foreshortening. Preferably, a defined feature is formed using a lithographic process, and the critical dimension scanning electron microscope is used to measure foreshortening of that feature. For example, the feature may be a line, and the critical dimension scanning electron microscope may be used to measure foreshortening of the line. Also, the feature may be two arrays of lines, and the critical dimension scanning electron microscope may be used to measure the separation distance between the arrays. That separation distance may be used to determine a focus of the lithographic process.

Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Abstract: A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conductive wires/studs in the first insulative layer. A lower portion of each damascene conductive wire/stud is in contact with an electronic device (e.g., a field effect transistor), or a shallow trench isolation, that is within the substrate layer. A top portion of the first insulative layer is removed, such as by etching, such that an upper portion of the damascene conductive wires/studs remain above the first insulative layer. A metallic capping layer is formed on the upper portions of the damascene conductive wires/studs such that the metallic capping layer is in conductive contact with the damascene conductive wires/studs.

Abstract: A method of forming a damascene structure, and the structure so formed, using a sacrificial conductive layer to provide a uniform focus plane for the photolithography tool during formation of circuit features. In particular, a metal layer is provided between the insulative layer and the photoresist, upon which the capacitive sensors of the photolithography tool focus during the formation of the circuit features, namely, troughs and vias.

Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.