Abstract: A semiconductor device having borderless contacts thereby providing a device having a reduced overall size. In particular, the device includes a plurality of shallow trench isolations and a plurality of dielectric isolations thereon to separate the adjoining device components and prevent shorts. Sidewall spacers surrounding and extend slightly above the device gates and dielectric isolations to further prevent shorts. A layer of conductive material atop each gate and diffusion region provides for coplanar contact surfaces. A layer of silicide beneath select regions of the conductive layer enhance electrical conductivity within the device. An internal wireless interconnection to electrically connect diffusion regions of different logic devices within the structure is also provided.

Abstract: A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness.

Abstract: A method for the control of wafer surface temperatures during post exposure bake on hot plates of wafers which carry integrated circuits. Also disclosed is a method of maximizing image size uniformity for integrated circuits through the zonal control of temperatures of hot plates during post exposure bake processes for effectively modulating the wafer surface temperatures. Images within a semiconductor wafer integrated circuit line pattern are repeated to process a wafer through the photolithographic patterning process, including post exposure baking, to measure the image linewidths and compare these with an experimentally derived correlation chart; for instance, PEB temperature vs. linewidth for a given or specified photomasking process.

Abstract: A method and apparatus for positioning a wafer in an electron beam lithography system. This method includes the steps of positioning a scanned probe microscope in the lithography system, and determining the distance between a preset location on the scanned probe microscope and a reference position in the lithography system. The wafer is brought into physical contact with that preset location, and then the wafer is moved a predetermined distance from the preset location on order to position the wafer at the desired focal plane in the lithography system.

Abstract: A method for drying one or more workpieces. The method includes the use of a chemically reactive additive to remove contaminants from the wafer surface during processing. In particular, during processing, a wafer is rinsed in a liquid bath and subsequently exposed to a chemically reactive additive. The chemically reactive additive creates a surface tension gradient that physically and chemically alters the properties of the film of the rise liquid so that the liquid and any contaminants contained therein are removed from the wafer surface.

Abstract: A non-volatile memory cell having a oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap diffusion region is obtained by forming a film stack on a surface of a substrate, said film stack comprising at least a floating gate oxide layer, a floating gate polysilicon later, an oxide layer and a nitride layer; forming an opening in said film stack so as to expose a portion of said floating gate polysilicon layer; forming oxide spacers in said opening; forming an oxide-nitride-oxide capacitor in said opening; forming polysilicon spacers on said oxide-nitride-oxide capacitor; providing a contact hole in said opening so as to expose a portion of said substrate; forming an oxide liner on exposed sidewalls of said contact hole; forming a source region in said substrate; forming oxide spacers from said oxide liner, wherein during the forming a portion of said substrate is re-expose; filling said opening and contact hole with doped polysilicon; and planarizing down to said nitride layer of said film stack.

Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.

Abstract: An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube.

Abstract: Robust alignment marks which are substantially resistant to degradation caused by semiconductor device fabrication steps are disclosed. The new alignment marks use a series of geometrical shapes that are staggered in respect to each other to achieve more left and right edges providing a checkerboard alignment mark. The geometrical shapes have a size that is selected so as to be within the resolving capability of the exposure tool, yet smaller than the resolving capability of the alignment system. The small staggered geometrical shapes provide a more symmetrical signal which is more resistant to variability in prior processing steps than the standard mark design.

Abstract: An apparatus and method are provided for cleaning (removing) contaminating particles and/or films from substrate surfaces such as semiconductor wafers during the fabrication process for making electronic components. The method and apparatus use a liquified gas contained in a distributor which has been energized with megasonic energy in the distributor and the energized liquefied gas directed as a stream against the surface to be cleaned from an outlet distribution nozzle of the distributor. The stream is preferably impinged on the substrate surface at an acute angle. The preferred liquified gas is carbon dioxide.

Abstract: A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the substrate using the oxide layer and the nitride layer, removing the silicon nitride layer, ion implanting dopant ions using the original oxide layer as a screen, into the substrate, and removing the oxide layer and forming a gate oxide layer over the substrate. Another method of forming an active area of a semiconductor device, includes using a pad oxide, remaining after removing a film layer thereover of an oxide/film mask stack, for a screen layer for well implants formed in the substrate, removing the oxide layer and forming a gate oxide over the substrate, following defining the well implants, without using a sacrificial oxide.

Abstract: An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.

Abstract: A photo resist composition contains a polymer resin, a first photo acid generator (PAG) requiring a first dose of actinic energy to generate a first photo acid, and a photo base generator (PBG) requiring a second dose of actinic energy, different from the first dose, to generate a photo base. The amounts and types of components in the photo resist are selected to produce a hybrid resist image. Either the first photo acid or photo base acts as a catalyst for a chemical transformation in the resist to induce a solubility change. The other compound is formulated in material type and loading in the resist such that it acts as a quenching agent. The catalyst is formed at low doses to induce the solubility change and the quenching agent is formed at higher doses to counterbalance the presence of the catalyst. Accordingly, the same frequency doubling effect of conventional hybrid resist compositions may be obtained, however, either a line or a space may be formed at the edge of an aerial image.

Abstract: A method for removing a formation of oxide of titanium that is generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65° C. combined with a 3 minute period of application.

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

Abstract: A method for introducing dopants into a semiconductor device using doped germanium oxide is disclosed. The method includes using rapid thermal anneal (RTA) or furnace anneal to diffuse dopants into a substrate from a doped germanium oxide sacrificial layer on the semiconductor substrate. After annealing to diffuse the dopants into the substrate, the germanium oxide sacrificial layers is removed using water thereby avoiding removal of silicon dioxide (SiO2) in the gates or in standard device isolation structures, that may lead to device failure. N+ and p+ sources and drains can be formed in appropriate wells in a semiconductor substrate, using a singular anneal and without the need to define more than one region of the first doped sacrificial layer. Alternatively, annealing before introducing a second dopant into the germanium oxide sacrificial layer give slower diffusing ions such as arsenic a head start.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a first side, and a second side opposite the first side. A bit-line diffusion region couples the first end of the mesa structure to a bit-line contact. A storage node diffusion region couples the second end of the mesa structure to the signal storage node. The word line controls a channel formed in the mesa structure through a gate which is formed upon the first side, the second side, and the top of the mesa structure. A sub-minimum width of the mesa structure allows full depletion to be easily achieved, resulting in volume inversion in the channel.

Abstract: A composition used to form an acid sensitive antireflective coating (ARC) includes a water soluble resin and a cross-linker. Radiation adsorptive components may be provided as part of the resin or, more preferably, as a separate dye. Being acid sensitive, selected portions of an ARC formed from the composition may be removed by a suitable reversal of the cross-linking followed by a develop step, preferably with an aqueous developer, more preferably de-ionized water. The water soluble resin is preferably hydroxystyrene-sulfonated styrene copolymer, poly(2-isopropenyl-2-oxazoline), or poly(acrylic acid), the cross-inker is preferably an acetal diacid or a water soluble divinyl ether, and the dye is preferably 9-anthracene methanol or a squaric acid derivative.

Abstract: A method of forming oxide and gate oxide areas of differing thicknesses. The processes disclosed include using an electromagnetic wave light at differing exposure durations and/or different energy levels to create oxide of differing thicknesses on a layer. The electromagnetic wave is preferably a laser.