Abstract: A method of implementing a new reticle for manufacturing semiconductors on a wafer which involves performing measurements on the reticle and assigning an initial exposure dose by using a predetermined algorithm. The exposure control system utilizes reticle CD data for automatically calculating reticle exposure offset values, i.e. reticle factors. A correlation of reticle size deviations to calculated reticle factors is used to derive a reticle factor for the new reticle. The derived reticle factor is then used to predict an initial exposure condition for the new reticle which is applied to the lithography tool for achieving a wafer design dimension.

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: A method of fabricating a bipolar transistor. The method comprising: forming an emitter opening in a dielectric layer to expose a surface of a base layer; performing a clean of the exposed surface, the clean removing any oxide present on the surface and passivating the surface to inhibit oxide growth; and forming an emitter layer on the surface after the performing a clean.

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.

Abstract: A method for limiting divot formation in shallow trench isolation structures. The method includes: providing a trench formed in a silicon region with a deposited oxide; oxidizing a top layer of the silicon region to form a layer of thermal oxide on top of the silicon region; and selectively etching the thermal oxide with respect to the deposited oxide.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: A method for making electrical contacts to device regions in a semiconductor substrate, and the resulting structure, is presented. A first set of borderless contacts is initially formed. This first set of contacts is then contacted by a second series of smaller, upper-level contacts. The second set of contacts also contact the gate of the device. The structure which results has a form wherein there are stacked contacts to the diffusion layer, and a single level contact to the device gate. The structure further provides local interconnectability over gate structures.

Abstract: A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.

Abstract: Photolithography tools have alignment systems for aligning a level to be printed with a level already on the wafer. Commonly a photolithography tool has several alignment systems Also, wafers may have several alignment marks, and the various alignment systems may be capable of reading several of the alignment marks. The present invention provides a method of selecting the alignment system-alignment mark combination that gives the most accurate alignment to a previous level. The inventors found that residual errors provide a metric by which to evaluate alignment system-alignment mark combinations. The combination with the least residual error is selected. Alternatively data for actual overlay measurements is compared with alignment data for each alignment system-alignment mark combination, and the combination that has the best correlation to the overlay data is selected.

Abstract: A method of forming a diffusion region in a silicon substrate having low-resistance, acceptable defect density, reliability and process control comprising the steps of: (a) subjecting a silicon substrate to a first ion implantation step, said first ion implantation step being conducted under conditions such that a region of amorphized Si is formed in said silicon substrate; (b) subjecting said silicon substrate containing said region of amorphized Si to a second ion implantation step, said second ion implantation step being carried out by implanting a dopant ion into said silicon substrate under conditions such that the peak of implant of said dopant ion is within the region of amorphized Si; and (c) annealing said silicon substrate under conditions such that said region of amorphized Si is re-crystallized thereby forming a diffusion region in said silicon substrate is provided.

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract: A microlithography mask for producing equal size features in a substrate. A first region exposes a first portion of the substrate corresponding to a first feature that is to be formed on the substrate. At least one compensating region in the vicinity of the first region partially exposes the first portion of the substrate and a second portion of the substrate corresponding to a second feature, wherein the second feature is to be removed from the substrate.

Abstract: A method for selectively heating a substrate without damaging surrounding regions of the substrate. In particular, the invention provides for a method of selectively activating doped regions of a semiconductor device without damaging surrounding doped and activated regions. Specifically, the invention provides a laser anneal which activates locally doped regions, while surrounding doped and activated regions are protected using a reflective mask.

Abstract: A microlithography mask for producing equal size features in a substrate. A first region exposes a first portion of the substrate corresponding to a first feature that is to be formed on the substrate. At least one compensating region in the vicinity of the first region partially exposes the first portion of the substrate and a second portion of the substrate corresponding to a second feature, wherein the second feature is to be removed from the substrate.

Abstract: Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: A method for improving the crosstalk and time-of-flight performance for signals in an integrated circuit with respect to the package-related wiring. I/O pads in the package-related wiring of a logic design meeting specified crosstalk and time-of-flight constraints are identified using a software tool. The tool produces a graphical display in which the identified I/O pads are highlighted. The tool enables a user to graphically manipulate the display to assign, i.e., establish an electrical connection, between I/O circuits corresponding to the signals and the highlighted I/O pads.

Abstract: A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.