Patents Represented by Attorney, Agent or Law Firm William D. Sabo
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Patent number: 6650021Abstract: A recessed bond pad within an electronic device on a substrate, and associated method of fabrication. The electronic device includes N contiguous levels of interconnect metallurgy, with level N coupled to the substrate. A first group of metallic etch stops is formed at level M≦N, and a second group of metallic etch stops is formed at level M−1. The second group conductively contacts the first group in an overlapping multilevel matrix pattern. A recessed copper pad is formed at level K≦M−2. A cylindrical space that encloses the metal pad encompasses levels 1,2, . . . , M−1 above the first group, and levels 1,2, . . . , M−2 above the second group. Dielectric material in the cylindrical space is etched away, leaving a void supplanting the etched dielectric material, and leaving exposed surfaces of the cylindrical space. The copper pad is exposed and recessed within the cylindrical space.Type: GrantFiled: December 3, 2001Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Anthony K. Stamper, Sally J. Yankee
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Patent number: 6649935Abstract: A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized seminconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.Type: GrantFiled: February 28, 2001Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Jack Allan Mandelman, William Robert Tonti, Li-Kong Wang
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Patent number: 6642584Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: GrantFiled: January 30, 2001Date of Patent: November 4, 2003Assignee: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Patent number: 6638629Abstract: A method and structure for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across a wafer surface. A substrate that includes a semiconductor material and a first dopant, has an amorphous layer formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. Heating of the wafer at 450 to 625 degree C. recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.Type: GrantFiled: July 22, 2002Date of Patent: October 28, 2003Assignee: International Business Machines CorporationInventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
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Patent number: 6635543Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.Type: GrantFiled: December 31, 2002Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park, William R. Tonti
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Patent number: 6634371Abstract: An apparatus for drying one or more workpieces. The apparatus includes the use of a chemically reactive additive to remove contaminants from the wafer surface during processing. In particular, during processing, a wafer is rinsed in a liquid bath and subsequently exposed to a chemically reactive additive. The chemically reactive additive creates a surface tension gradient that physically and chemically alters the properties of the film of the rinse liquid so that the liquid and any contaminants contained therein are removed from the water surface.Type: GrantFiled: May 14, 2001Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Richard Hilliard Gaylord, III, Frederick William Kern, Jr., Donald Joseph Martin, Harald Franz Okorn-Schmidt, John Joseph Snyder, William Alfred Syverson
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Patent number: 6614124Abstract: An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.Type: GrantFiled: November 28, 2000Date of Patent: September 2, 2003Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Chung Hon Lam, Randy William Mann
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Method to define and tailor process limited lithographic features using a modified hard mask process
Patent number: 6610607Abstract: A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls of the mask. The pattern of the mask and spacers is then transferred to an underlying layer.Type: GrantFiled: May 25, 2000Date of Patent: August 26, 2003Assignee: International Business Machines CorporationInventors: Douglas S. Armbrust, Dale W. Martin, Jed H. Rankin, Sylvia Tousley -
Patent number: 6610585Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.Type: GrantFiled: February 26, 2002Date of Patent: August 26, 2003Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, Bryant C. Colwill, Terence B. Hook, Dennis Hoyniak
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Patent number: 6605534Abstract: The present invention provides a method of selectively inhibiting the deposition of a conductive material within desired regions of a semiconductor device. A seed layer is rendered ineffective to the electroplating in select regions of the substrate, by either the removal or the poisoning of the seed layer in select regions.Type: GrantFiled: June 28, 2000Date of Patent: August 12, 2003Assignee: International Business Machines CorporationInventors: Dean S. Chung, David V. Horak, Erick G. Walton
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Patent number: 6606533Abstract: A method and an arrangement for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and adjust the exposure dose based on the path through the process, so as to render the output and resultant image size of each path identical to each other and close to a target value.Type: GrantFiled: October 12, 2000Date of Patent: August 12, 2003Assignee: International Business Machines CorporationInventor: Charles A. Whiting
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Patent number: 6597050Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.Type: GrantFiled: May 19, 2000Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: James Stuart Dunn, Peter Brian Gray, Kenneth Knetch Kieft, III, Nicholas Theodore Schmidt, Stephen St. onge
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Patent number: 6590290Abstract: A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insulating layer, and etching the etch stop layer to form an opening at a position over the first interconnect region. A second interconnect region is formed in contact with the first insulating layer and above the first interconnect region, a second insulating layer is formed over the first insulation layer and the etch stop layer, and an opening is formed in the second insulating layer overlapping the opening in the etch stop layer. The opening in the second insulating layer is extended through the first insulating layer and the openings in the first and second insulating layers are filled with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.Type: GrantFiled: March 22, 2000Date of Patent: July 8, 2003Assignee: International Business Machines CorporationInventors: John E. Cronin, Barbara J. Luther
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Patent number: 6590259Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.Type: GrantFiled: November 2, 2001Date of Patent: July 8, 2003Assignee: International Business Machines CorporationInventors: James W. Adkisson, Ramachandra Divakaruni, Jeffrey P. Gambino, Jack A. Mandelman
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Patent number: 6580140Abstract: A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600° C., wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600° C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer.Type: GrantFiled: September 18, 2000Date of Patent: June 17, 2003Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Edward C. Cooney, III, Jeffrey D. Gilbert, Robert G. Miller, Amy L. Myrick, Ronald A. Warren
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Patent number: 6576525Abstract: A damascene capacitor structure includes a recessed capacitor plate for preventing leakage and dielectric breakdown between the capacitor plates of the capacitor structure on the surface of the trenches and in the bottom corners of the trenches.Type: GrantFiled: March 19, 2001Date of Patent: June 10, 2003Assignee: International Business Machines CorporationInventor: Anthony K. Stamper
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Patent number: 6570209Abstract: A non-volatile memory cell having a oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap diffusion region is obtained by forming a film stack on a surface of a substrate, said film stack comprising at least a floating gate oxide layer, a floating gate polysilicon layer, an oxide layer and a nitride layer; forming an opening in said film stack so as to expose a portion of said floating gate polysilicon layer; forming oxide spacers in said opening; forming an oxide-nitride-oxide capacitor in said opening; forming polysilicon spacers on said oxide-nitride-oxide capacitor; providing a contact hole in said opening so as to expose a portion of said substrate; forming an oxide liner on exposed sidewalls of said contact hole; forming a source region in said substrate; forming oxide spacers from said oxide liner, wherein during the forming a portion of said substrate is re-expose; filling said opening and contact hole with doped polysilicon; and planarizing down to said nitride layer of said film stack.Type: GrantFiled: January 8, 2002Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventor: Chung Hon Lam
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Patent number: 6559030Abstract: A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.Type: GrantFiled: December 13, 2001Date of Patent: May 6, 2003Assignee: International Business Machines CorporationInventors: Thai Doan, Zhong-Xiang He, Michael P. McMahon
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Patent number: 6555859Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: GrantFiled: August 8, 2001Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: James William Adkisson, Charles Thomas Black, Alfred Grill, Randy William Mann, Deborah Ann Neumayer, Wilbur David Pricer, Katherine Lynn Saenger, Thomas McCarroll Shaw
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Patent number: 6555891Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.Type: GrantFiled: October 17, 2000Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park, William R. Tonti