Abstract: An illumination system includes optics capable of adjusting the size of a beam of light and adjusting the focus of the beam of light. Spot size control optics adjusts the overall size of the beam of light and separately adjusts the ellipticity of the beam, primarily in one dimension. Light from the spot size control optics passes to focus control optics that control the overall focus of the beam of light and adjust the astigmatism of the beam by altering the focus position of the beam of light in one dimension. The laser system, the spot size control optics and the focus control optics are within an enclosure. Actuators under remote control from outside of the enclosure adjust both of the spot size control optics and focus control optics in the thermal environment of the illumination system.

Abstract: A solid state laser includes a high absorption coefficient solid state gain medium such as Nd:YVO4 that is side pumped with a semiconductor laser diode array. The resonant cavity of the solid state laser is positioned so that the TEM00 mode is spaced from the face of the laser through which the laser is pumped by a distance sufficient to reduce diffraction losses but sufficiently near to allow coupling of pump light into the gain mode. The gain medium, the doping level of the gain medium, and the operating temperature of the pump laser are selected to efficiently couple pump light into the gain mode. The pump laser is positioned to side pump the gain medium without collimating or focusing optics between the pump laser and the face of the gain medium. A gap between the pump laser and the gain medium is empirically selected to match the angular extent of the pump laser output light to the height of the gain mode at the position of the gain mode fixed to optimize coupling and diffraction losses.

Abstract: A silicon on insulator (SOI) DRAM has a layer of buried oxide covered by a thin layer of crystalline silicon on the surface of a bulk silicon substrate. Field oxide regions are formed extending through the thin crystalline silicon surface layer and into contact with the buried oxide layer. Gate oxide layers, gate electrodes and source/drain regions for the transfer FETs of the DRAM are formed in and on the thin crystalline silicon surface layer in the active regions between the field oxide regions. A trench is opened through one of the source/drain regions of each of the transfer FETs. A layer of doped polysilicon is provided to line the trenches and is patterned to form at least a part of the bottom electrodes of the charge storage capacitors for the DRAM. The bottom electrodes are covered with a thin dielectric layer and an upper electrode of doped polysilicon is provided. Preferably, the trench for the bottom capacitor electrode extends through the buried oxide layer and may extend into the bulk silicon.

Abstract: A method is described for making an array of dynamic random access memory (DRAM) cells having both a trench and a stacked capacitor within each cell. The method involves forming a trench in the silicon substrate at the capacitor node contact area of the DRAM cell, and depositing an N+ doped polysilicon layer to form an N+/P diode capacitor in the trench. Another N+ doped polysilicon layer is deposited and anisotropically etched back over a patterned silicon nitride/silicon oxide layer in the trench areas to form the bottom electrodes of stacked capacitors with vertically extending sidewalls. An interelectrode dielectric layer is formed on the bottom electrodes and top electrodes are formed from a patterned N+ doped polysilicon layer to complete the array DRAM trench/stacked capacitors. The trench diode capacitor electrically connected in parallel with the stacked capacitor increase the cell capacitance. The vertical extensions on the stacked capacitor further increase the capacitance of the DRAM cell.

Abstract: A method of manufacture for flat-cell Mask ROM devices on a silicon semiconductor substrate covered with a first gate oxide layer comprises, forming a first conductor structure on the first gate oxide layer, forming a buried conductive structure within the substrate by ion implantation with a portion thereof in juxtaposition with the first conductor structure, etching away the exposed surfaces of the first gate oxide layer exposing portions of the semiconductor, forming a second gate oxide layer on the surface of the semiconductor, and forming a second conductor structure on the second gate oxide layer.

Abstract: Hemispherical-grained silicon (HSG-Si) is grown on polysilicon by plasma deposition. A wider range of substrate deposition temperatures can be used in the plasma deposition of HSG-Si than can be maintained in the low pressure chemical vapor deposition (LPCVD) of HSG-Si. The plasma deposition of HSG-Si can be performed in an electron cyclotron resonance chemical vapor deposition (ECR-CVD) system at input power levels ranging from 100-1500 W, at total pressures between 5-60 mTorr, and at substrate temperatures ranging from 200.degree.-500.degree. C. A mixture of silane and hydrogen gases at a dilution ratio of silane within the silane and hydrogen gas mixture H.sub.2 /(SiH.sub.4 +H.sub.2) between about 70-99% may be used in the ECR-CVD system. The polysilicon surface is cleaned of native oxides prior to plasma deposition of HSG-Si.

Abstract: A new method of forming a metal diffusion barrier layer is described. Semiconductor device structures are formed in and on a semiconductor substrate. At least one dielectric layer covers the semiconductor structures and at least one contact hole has been opened through the dielectric layer(s) to the semiconductor substrate. A metal diffusion barrier layer is now formed using the following steps: In the first step, a thin layer of titanium is deposited conformally over the surface of the dielectric layer(s) and within the contact opening(s) and annealed in a nitrogen atmosphere at a temperature of between about 580.degree. to 630.degree. C. for between about 20 to 120 seconds. The second step is to form stable and adhesive titanium compounds on the pre-metal dielectric layer as well as to form a low resistance silicide on the contact silicon by annealing at between about 800.degree. to 900.degree. C. for between about 5 to 60 seconds.

Abstract: A method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant.

Abstract: A DRAM memory capacitor is formed by depositing a layer of polysilicon on FOX and device areas. Form gate structures and S/D structures by etching through the oxide layer, so openings extend over a portion of the polysilicon layer of the gate structure and the FOX areas. Capacitor plates are formed next. Deposit a first plate into electrical and mechanical contact with one of the S/D structures and dope the first capacitor plate to a high level. Deposit a second plate doped to a low level, a third plate doped to a high level, and a fourth plate doped to a low level. Pattern the plates by etching so the remaining portions lie over planned capacitor areas, with the remainder removed by selective isotropic etching away of portions of the plates doped to a high level to provide fins by removal thereof from between plates doped to a low level.

Abstract: A new method of forming controlled voids within the intermetal dielectric and within the passivation layer of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the first patterned metal layer wherein the thickness of the intermetal dielectric layer is large enough so as to cause the formation of voids within the intermetal dielectric and wherein said voids are completely covered by said intermetal dielectric. A second layer of metallization is deposited over the intermetal dielectric and patterned. A passivation layer is deposited overlying the second patterned metal layer. The thickness of the passivation layer is large enough so as to cause the formation of voids within the passivation layer wherein said voids are completely covered by said passivation layer.

Abstract: A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric.

Abstract: In accordance with this invention, a method of manufacture of a semiconductor memory device comprises the following steps: forming field oxide structures on a semiconductor substrate, forming a gate oxide layer on exposed surfaces of the substrate, forming a first word line layer on the device, patterning the first word line layer by forming a first patterned mask mask with a first set of openings therein and etching the first word line layer through the openings in the first mask to form conductor lines, forming a first dielectric layer on the surface of the first word line layer on the device, forming a second word line layer on the first dielectric layer, patterning the second word line layer by forming a second patterned mask with a second set of openings therein and etching portions of the second word line layer therethrough, h) forming a second dielectric layer on the surface of the second word line layer on the device, and implanting ions of dopant into predetermined locations into the semiconductor su

Abstract: A structure and a process for forming an improved bonding pad which resists bond pad peeling of between the bonding pad layer and the underlying layers. The method comprises forming plurality of anchor pads on said substrate surface in a bonding pad area. Next, a first insulating layer is formed over said substrate surface and the anchor pads. Vias are formed through the first insulating layer. The vias are filled with a second metal layer making a connection to the anchor pads and the first insulating layer is covered in the bonding pad area with the second metal layer. It is important that the via holes have a smaller cross sectional area than the anchor pads so that the combination of the anchor pads and the second metal form small "hooks" into the first insulating layer that hold the second metal (bonding pad layer) to the underlying layer.

Abstract: The invention describes recessed source/drain regions formed in trenches in the substrate that provide a smooth surface topology, smaller devils and improved device performance. The recessed source/drain regions have two conductive regions: the first upper lightly doped region on the trench sidewalls, and the second lower region under the trench bottom. In addition, two buried layers are formed between adjacent source/drain regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the lower source/drain regions on the trench bottoms. The upper lightly doped source/drain region and the anti-punchthrough layer have the effect of increasing the punchthrough voltage without increasing the threshold voltage. The upper and lower source/drain regions lower the overall resistivity of the source/drain allowing use of smaller line pitches and therefore smaller devils.

Abstract: A structure and a process for forming an improved bonding pad which allows better bonding between a bond wire and a metal bonding pad. Stripes are formed on a substrate. A conformal dielectric layer, a conformal barrier layer and a metal layer are formed over the stripes. A passivation layer with a window is formed defining a bonding pad area. The stripes promote an irregular surface in the barrier and metal layers which reduce stress between the dielectric layer, the barrier layer and the metal layer. Also, the irregular surfaces increase the barrier metal adhesion to the dielectric layer, reduce bond pad peel off, and increase bonding yields.

Abstract: A shield structure is formed over each of the undoped or lightly doped polysilicon load devices of a 4T SRAM cell. The shield structure may be a metal such as aluminum, titanium or tungsten and serves to protect the undoped or lightly doped resistor within a polysilicon load device from charge-induced damage during ion implantation or plasma processing steps performed on the SRAM after formation of the polysilicon load device. The polysilicon load device is defined by depositing a layer of photoresist, exposing the photoresist through a master load mask, etching, and implanting into the exposed polysilicon. After the load device is formed, a dielectric layer is deposited and then a layer of conductive material is deposited. Dummy conductor structures are formed from the layer of conductive material using photolithography and the master load mask.

Abstract: A new method of forming an integrated circuit MNOS/MONOS device with suppressed off-cell leakage current is described. A silicon oxide layer is formed on the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon oxide layer and patterned. A first ion implantation is performed at a tilt angle to form channel stop regions in the semiconductor substrate not covered by the patterned silicon nitride layer wherein the channel stop regions partially extend underneath the patterned silicon nitride layer. The silicon substrate not covered by the patterned silicon nitride layer is oxidized to form field oxide regions within the silicon substrate wherein the channel stop regions extend under the full length of the field oxide regions. The patterned silicon nitride layer is removed. An insulating layer of silicon nitride/silicon oxide (NO) or silicon oxide/silicon nitride/silicon oxide (ONO) is deposited over the surface of the semiconductor substrate.

Abstract: The invention describes the fabrication and use of a sub-resolution phase shift mask. The mask is formed using a single alignment step with all other alignment steps being accomplished by self alignment. This self alignment is made possible by using vertical anisotropic etching of an opaque material layer to form opaque spacers at the pattern edges of phase shifting material. The opaque spacers combine with phase shifting and other opaque regions of the mask to provide improved image resolution and depth of focus tolerance at the surface of an integrated circuit wafer.

Abstract: A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon dioxide film, ion implanting ions into said substrate adjacent to at least some of said silicon nitride patterns for well regions of a first polarity, forming a mask over said device, and deeply ion implanting with ions of opposite polarity into well regions of opposite polarity.