Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: The invention relates to an improved MOSFET device structure for use in ultra large scale integration and the method of forming the device structure. A local punchthrough stop region is formed directly under the gate electrode using ion implantation. The local punchthrough stop region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local punchthrough stop region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. The source and drain junction capacitances are also reduced. The invention can be used in either N channel or P channel MOSFET devices. The invention can be used with a conventional source/drain structure as well as a double doped drain structure and a light doped drain structure.

Abstract: A method provides for manufacturing an MOSFET semiconductor device with an array of semiconductor structures on a lightly doped semiconductor substrate. A mask is formed upon the substrate with openings therein. An oxide is formed in the semiconductor substrate. The oxide extends down into sunken regions in the substrate through the openings in the mask. The oxide is removed from the substrate opening the sunken regions in the substrate. Spacers are formed in the openings in the mask forming smaller openings in the spacers. Then, ions are introduced into the substrate below the sunken regions through the smaller openings to form channel stop regions. Then the spacers are removed. A second oxide is formed in the sunken regions.

Abstract: Device isolation is provided for a MOSFET circuit by providing channel stop regions comprising a distribution of dopants localized beneath and adjacent to corresponding field oxide regions. Channel stop regions are not formed under the channel regions of the MOSFETs and are selectively formed under the narrower field oxide regions which are most likely to provide inadequate device isolation. The channel stop regions are formed subsequent to the formation of field oxide regions, beginning by forming polysilicon spacers so that the polysilicon spacers extend over the bird's beak regions of the field oxide regions. Next, a channel stop mask having openings over selected field oxide regions is formed. Trenches are etched near the center of the exposed field oxide regions, leaving approximately 500 .ANG. of oxide on the bottom of the trench. Ions are implanted through the bottom of the trenches to form channel stop regions beneath the field oxide regions.

Abstract: A semiconductor device is formed on a substrate lightly doped with a dopant, a source region and a drain region in the substrate on the surface thereof, a dielectric layer deposited upon the substrate, a first floating gate layer formed on the dielectric layer, a second floating gate layer formed on the the first floating gate layer, a second dielectric material deposited upon the surface of the first floating gate electrode, a control gate electrode deposited upon the surface of the additional dielectric material, and means for applying a voltage to the control gate electrode.

Abstract: A new method of fabricating a polycide gate is described. A gate polysilicon layer is provided a gate oxide layer on the surface of a substrate. A thin conducting diffusion barrier is deposited overlying the gate polysilicon layer. A of tungsten silicide is deposited overlying the thin diffusion barrier layer wherein a reaction gas in the deposition contains fluorine atoms and wherein fluorine atoms are incorporated into the tungsten layer. The gate polysilicon, thin conducting barrier, and tungsten silicide layers are patterned form the polycide gate structures. The wafer is annealed complete formation of the polycide gate structures wherein number of fluorine atoms from the tungsten silicide layer into the gate polysilicon layer are minimized by presence of the thin conducting diffusion barrier layer wherein because the diffusion of the fluorine atoms is the thickness of the gate oxide layer does not This prevents the device from degradation such as voltage shift and saturation current descrease.

Abstract: A manufacturing system for individually processing semiconductor wafers through a plurality of processing stations. The system has a plurality of processing stations, a multilevel track system that interfaces with the processing stations, and guided transport vehicles that operate on the track system to move individual wafers in wafer carriers between the stations. The carriers have a storage memory that contains the required process sequence and the capability to remember the completed process steps.

Abstract: A new photolithographic process using the method of photoresist double coating to fabricate fine lines with narrow spacing is described. A layer to be etched is provided overlying a semiconductor substrate. The layer to be etched is coated with a first layer of photoresist and baked. The first photoresist layer is exposed to actinic light through openings in a mask and developed to produce the desired first pattern on the surface of the first photoresist wherein the openings have a minimum width of the resolution limit plus two times the misalignment tolerance of the photolithography process. The layer to be etched is coated with a second photoresist layer where the layer to be etched is exposed within the openings in the first photoresist layer.

Abstract: A field oxide structure having a reduced number of defects is described. A field oxide mask is formed over a substrate having openings which expose portions of the substrate where the field oxide structures are to be formed. Silicon nitride spacers are formed on the sidewalls of the openings. Channel stop ions are selectively implanted through the opening into the substrate and then the thick field oxide structures are formed. Stress-generated crystalline defects are formed underlying the field oxidation regions at the edges of the openings. The silicon nitride spacers are removed. An additional source/drain ion implantation is performed by implanting ions to doped regions in the substrate deep enough into the substrate so that the crystalline defects are enclosed within the implanted regions to reduce junction leakage. The silicon dioxide, silicon nitride, and pad silicon oxide layers are removed to complete the field oxide structure.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

Abstract: A method is described for making an array of dynamic random access memory (DRAM) cells having a trench/stacked capacitor within each cell. The method involves forming trenches in the silicon substrate at the capacitor node contact areas of the DRAM cells, and using liquid phase deposition (LPD) of silicon oxide in the trenches to form oxide plugs that extend upward into the openings in the photoresist mask used to etch the trenches. After removing the photoresist, polysilicon sidewall spacers are formed on the LPD oxide plugs. The sidewall spacers become part of the stacked capacitor structures. Another patterned polysilicon layer is used to form the array of storage-node electrodes for the stacked capacitors, and also serve as the storage-node electrodes for the trench capacitors. Conventional methods are used to complete the array of trench/stacked capacitors by depositing an interelectrode dielectric layer and then forming the polysilicon top electrodes.

Abstract: An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.

Abstract: An integrated circuit incorporates a metal wiring line layout scheme which reduces the likelihood of incorporating holes through the passivation layer which covers the metal wiring line. Wiring lines are formed so as to have constant separation around bends in the wiring lines, typically by also increasing the width of the wiring lines around the bends. This layout reduces the likelihood of forming holes in the passivation layer between wiring lines. Holes are prevented near the ends of wiring lines either by providing dummy wiring lines offset from the ends of the wiring lines or by reducing the height of the wiring lines at the ends of the wiring lines. The ends of wiring lines can be sloped by providing dummy vias at the ends of the wiring lines and forming the ends of the wiring lines in the dummy vias.

Abstract: A method of forming bipolar ROM device on a semiconductor substrate comprises forming a collector region by doping with a dopant of a first polarity, forming an array of common base regions by doping with a dopant of an opposite polarity, forming a plurality of emitter regions selectively in the base regions by doping with a dopant of first polarity and diffusing the dopant into the emitter regions from doped conductors, which conductors are formed as an array of conductors disposed orthogonally relative to the array of common base elements. The conductors are connected to emitter regions traversed thereby and are isolated from other regions by dielectric layers selectively formed over the other regions to prevent diffusion of dopant therethrough to prevent formation of such emitter regions.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.

Abstract: A process for manufacturing bonding pad adapted for use with an aluminum wire that resists stresses that would otherwise peel the pad from the substrate. The pad has a polysilicon layer adhered to an insulating layer on a semiconductor substrate, a overlying refractory metal polycide layer, a second polysilicon layer, a refractory metal layer, and a thick aluminum alloy bonding pad.

Abstract: A ROM semiconductor device and a method of manufacturing that device on a semiconductor substrate comprises the steps of forming a blanket word line layer over the device with a reverse word line mask over the word line layer, the word line mask comprising a parallel array of mask strips, forming a ROM code mask over the reverse word line mask, the ROM code mask having a ROM code opening centered between a pair of the mask strips. A code implant dopant is ion implanted through the ROM code opening down into a doped region in the substrate below the ROM code opening. The ROM code mask is removed. A word line mask is formed comprising complementary mask strips between the mask strips of the reverse word line mask followed by removal of the reverse word line mask, etching the word line layer to form a parallel array of word lines beneath the complementary mask strips, and forming a blanket layer of dielectric material over the device.

Abstract: A semiconductor transistor device on a semiconductor substrate comprises source/drain regions in the substrate. A tunnelling oxide layer combined with a gate oxide layer covers the substrate including the heavily doped regions. A pair of floating gates above the tunnelling oxide layer form source/drain relationships with three centrally located ones of the heavily doped regions. A first dielectric layer covers the floating gates. A set of control gates cover the first dielectric layer. A second dielectric layer covers the control gates. The floating gate structure, the first dielectric layer, the control gate layer and the second dielectric layer all forming with the three centrally located heavily doped regions an adjacent pair of stacked EEPROM transistor structures, with two additional, adjacent, outboard heavily doped regions.

Abstract: A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.