Abstract: A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide.

Abstract: A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.

Abstract: A method is provided for fabricating a split gate flash EPROM device. A stack is formed of a first dielectric layer on the lightly doped semiconductor substrate followd by a floating gate, a first intergate dielectric layer, an intermediate control gate layer, an isolating layer over the intermediate control gate layer, and a floating gate mask on the device. The stack is formed by etching in the pattern of the floating gate. A split gate mask is formed followed by ion implanting dopant into source/drain regions in the substrate adjacent to the mask with one source/drain region self aligned with the stack and the other spaced away from the other side of the stack. After mask removal, a second intergate dielectric layer blanket is formed with an etch back forming sidewalls next to the stack by etching away exposed portions of the first dielectric layer, forming a second dielectric layer on the substrate and the source/drain regions.

Abstract: A process for manufacturing an LDD type of FET, based on the salicide process, is described. Said process does not lead to short circuits between the drain region and and the main body of the FET through the buried contact. The process is based on the use of Liquid Phase Deposition (LPD) as the method for growing the oxide layer from which the spacers are formed. Since oxide layers formed through LPD will deposit preferentially on silicon and silicon oxide surfaces relative to photoresist surfaces, the areas in which the LPD layer forms are readily controlled. This feature allows the buried contact layer to be replaced by an extended drain region which can be connected to other parts of the integrated circuit (by the salicide process) without the danger of shorting paths being formed therein.

Abstract: A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.

Abstract: A liquid crystal display having an improved angular distribution for emerging radiation is described, together with a method for manufacturing it. This was achieved by forming patterns, one per pixel, of concentric annuli in one of the orientation layers and radial spokes in the other orientation layer. This guarantees that there is a wide range in the orientations of the twisted nematics, leading to an improved angular distribution for the emerging radiation. The invention is applicable to both monochrome as well as color displays and may also be used as a way to adjust, during manufacturing, the angular distribution of the emerging light.

Abstract: A novel process for depositing amorphous silicon has been described. The process features the homogeneous reaction of, decomposition of SiH2 and deposition of amorphous silicon, in a horizontal LPCVD reaction chamber. The SiH2 is produced by initially breaking down SiH4 in a heated autoclave apparatus, and then transferring the SiH2 to the LPCVD system through heated feed lines. This homogeneous process results in excellent thickness and resistivity uniformity for wafers placed along the horizontal axis of the LPCVD chamber.

Abstract: A method of forming an EEPROM memory cell on a semiconductor substrate, comprises forming a first dielectric layer on the substrate, a gate electrode of a select transistor and a first layer of a floating gate electrode of an EEPROM device on the dielectric layer, ion implanted source/drain regions in the substrate adjacent to the gate electrode and the first layer of the floating gate electrode proximate to at least the periphery of the gate electrode and the first layer of the floating gate electrode. The central region of the ion implanted regions is between the gate electrode and the first layer of the floating gate electrode.

Abstract: An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line.

Abstract: A device and a method of formation on a substrate of a semiconductor interconnection via structure for semiconductor devices is provided. Initially, form a first metal layer on the substrate, a first dielectric layer upon the first metal layer, and a mask upon the dielectric layer with a metal etching pattern therein. Then, etch through the first dielectric layer and the first metal layer to the substrate forming trenches between metal lines formed from the first metal layer covered with the dielectric layer. Next, form a first etch stop layer upon the surface of the the first dielectric layer and planarize it, a second dielectric layer above the etch stop layer, and a second etch stop layer on the second dielectric layer. Then, pattern the second dielectric and the second etch stop layer and etch to form a via hole down to a surface of the first metal layer. Then, form a second metal layer and a metal plug in the via hole extending into contact with the first metal layer.

Abstract: A memory cell layout and method of forming a 6 transistor SRAM memory cell that achieves a reduced cell area using uncomplicated fabrication steps. In one embodiment, a six transistor (6/T) SRAM cell has two horizontal thin-film transistor (T5, T6) as load transistors, two transfer transistors (T1, T2), two latch transistors (T3, T4) and two current nodes (38, 40). In this structure all six transistors are formed in the substrate and a single polysilicon layer.

Abstract: The invention describes the fabrication and use of a sub-resolution phase shift mask. The mask is formed using a single alignment step with all other alignment steps being accomplished by self alignment. This self alignment is made possible by using vertical anisotropic etching of an opaque material layer to form opaque spacers at the pattern edges of phase shifting material. The opaque spacers combine with phase shifting and other opaque regions of the mask to provide improved image resolution and depth of focus tolerance at the surface of an integrated circuit wafer.

Abstract: A read-only-memory having a plurality of very narrow, closely spaced gate electrodes spanning the distance between source and drain regions. The gate electrodes consist of first and second alternating polycrystalline silicon lines having vertical sidewalls. The first lines have tapered sidewall spacers. The second lines are entirely contained between the first lines without overlap of the first lines.

Abstract: A new method of fabricating a high coupling ratio Flash EEPROM memory cell is achieved. A layer of silicon dioxide is provided over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. The silicon dioxide layer not covered by the patterned silicon nitride layer is removed, thereby exposing portions of the substrate. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. Ions are implanted into the substrate using the silicon nitride layer and spacers as a mask to form implanted regions within the semiconductor substrate. The semiconductor substrate is oxidized where the implanted regions have been formed leaving the thin tunnel oxide only under the silicon nitride spacers. The silicon nitride layer and spacers are removed.

Abstract: This is a method of manufacturing a multiple state MASK ROM semiconductor device on a P-type semiconductor substrate. The substrate includes an array of parallel buried bit lines oriented in a first direction. The process includes forming a gate oxide layer over the substrate including the buried bit lines; word lines over the gate oxide layer oriented orthogonally to the direction of the array of bit lines. Then form a first patterned implant mask over the device with a first set of openings through the mask. Ion implant dopant of a first dosage level through the openings in the mask to form implant doped regions of a first dosage level in the substrate. Form a second patterned implant mask over the device with a second set of openings through the mask. Then ion implant a dopant of a second dosage level through the openings in the mask to form implanted doped regions of a second dosage level in the substrate, the second dosage level being substantially different from the first dosage level.

Abstract: An improved structure and process of fabricating a programmable and erasable read only memory device wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide region is removed forming a depression in the surface. Impurity ions are implanted into the depression forming a lightly doped source region. A tunnel oxide layer is formed on the substrate surface. Next, the floating gate layer is formed on the tunnel oxide layer which at least partially overlies the lightly doped source region. A gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact opening are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrical programmable memory device.

Abstract: A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made via a self-alignment technique. The collector region of the transistor is contacted through the floor of the trench while the base region of the transistor is contacted in a region that surrounds the trench. The described method is compatible with the simultaneous manufacture of FET devices on the same chip.

Abstract: This invention describes a diving channel device structure and a method of forming the diving channel device structure using deep vertical trenches formed in a silicon substrate crossing shallow vertical trenches formed in the same silicon substrate. The deep vertical trenches are filled with a first heavily doped polysilicon to form the sources and drains of field effect transistors. The shallow vertical trenches are filled with a second highly doped polysilicon to form the gates of the transistors. The device structure provides reduced drain and source resistance which remains nearly constant when the device is scaled to smaller dimensions. The device structure also provides reduced leakage currents and a plane topography. The device structure forms a large effective channel width when the device is scaled to smaller dimensions.

Abstract: A method of manufacturing an improved Read-Only-Memory (ROM) device, was achieved. The array of programmed ROM cells composed of field effect transistors (FETs) are fabricated having improved bit lines with lower resistance. The method utilizes the selective deposition of silicon oxide by a method of Liquid Phase Deposition (LPD) to form a thick insulating oxide layer over the gate oxide of the FET in the coded memory cells. The thick insulating oxide raises the threshold voltage of the FET, preventing the FET from turning on when a gate voltage is applied. The coding using a thick insulating oxide eliminates the need to code the ROM memory cells by ion implantation, and thereby prevents the counter-doping of the bit lines which results in the high bit line resistivity that degrades circuit performance.

Abstract: A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.